EP0567932A2
Expired / Lapsed
EP
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Video memory system with double multiplexing of video and motion samples in a field memory for motion adaptive compensation of processed video signals
Assignee: Technicolor USA Inc
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Filing: 1993-04-22
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Granted: —
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Expires: 2013-04-22
Abstract
Abstract Plural signal delays in a progressive scan system are provided by a field memory (205) having double multiplexing within a video line to provide compacted data samples including interleaved pixels in a first time interval representing field and frame delayed pixel samples and compressed motion data in a second time interval representing frame motion delayed by a field interval. Advantageously, the double multiplexing avoids the need for multiple field delays which otherwise would be required for providing field delayed video, frame delayed video, and field delayed motion signals in motion adaptive systems designed for accurate reproduction of small fast moving objects in a displayed image.
Inventors
- 👤 Todd J. Christopher
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 23:16
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/14; H04N5/144; H04N9/00; H04N9/77; H04N9/78; H04N7/00; H04N7/01; H04N7/0117; H04N7/012
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
192 words
Memory apparatus comprising, in combination: a source for providing video samples (I-H VIDEO) and motion samples (MOTION IN); a field memory (205); first circuit means (200,202) coupled to said field memory for interleaving said video samples supplied to said memory (I-H VIDEO) with video samples (263H VIDEO OUT) output from said memory for storage in said field memory during a first time interval of each video line; said first circuit means having first and second outputs (54,56) providing, respectively, video samples that have passed through the field memory one time to provide a field delayed video output signal (263H VIDEO OUT) and providing a frame delayed output signal (525H VIDEO OUT) for video samples having passed through said field memory two times; characterized by second circuit means for time compressing and storing motion data associated with a previous line of video samples in a second time interval of each video line in said field memory; said second circuit means being coupled to an output of said field memory for recovering the time compressed motion samples and for decompressing the samples to provide a field delayed motion indicating output signal (263H MOTION OUT).
Claim 2
Dependent Claim
85 words
The memory apparatus of claim 1 characterized in that said first circuit means (200,202) comprises: a first multiplexor (200) responsive to a timing signal (FS/2) for selectively coupling one of said video samples (1-H VIDEO) and said field delayed output signal (263H VIDEO OUT) to an input of said field memory (205); and a demultiplexor (202) responsive to said timing signal for selectively coupling an output of said field memory to one of said first (54) and second (56) outputs of said first circuit means.
Claim 3
Dependent Claim
126 words
The memory apparatus of claim 2 characterized in that said second circuit means (204,206,208,210) comprises: a buffer memory (210) having an output (60) for providing said field delayed motion indicating signal (263H MOTION OUT); a second multiplexor (206) for selectively coupling one of said motion samples (MOTION IN) and an output of said field memory to an input of said buffer memory in response to a blanking signal (HB) indicating the occurrence of a horizontal blanking interval included in a video signal from which said video samples are derived; and a third multiplexor (204) for selectively coupling one of said output of said buffer memory and an output of said first multiplexor (200) to said input of said field memory in response to said blanking signal.
Claim 4
Dependent Claim
47 words
The memory apparatus of claim 3 characterized in that said second circuit means further comprises a fourth multiplexor (208) for selectively coupling one of first (FC) and second (SC) clock signals to a control input of said buffer memory (210) in response to said blanking signal (HB).
Claim 5
Dependent Claim
59 words
The memory apparatus of claim 4 characterized in that said first clock signal (FC) exhibits a higher frequency than said second clock signal (SC); and said fourth multiplexor (208) couples said first clock signal to said buffer memory for compressing said motion samples and couples said second clock signal to said buffer memory (210) for expanding said motion samples.
Claim 6
Dependent Claim
31 words
The memory apparatus of claim 2 characterized in that said timing signal (FS/2) is derived from a sampling signal (FS) used to sample a video signal to produce said video samples.
References Cited (Backward Citations)
No citation records indexed.
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