Packaged semiconductor device having a flange at its side surface and its manufacturing method

Claim 1

A method of manufacturing a packaged semiconductor device comprising the steps of: providing a lead frame with an electrically insulating strip member, said lead frame having a chip mounting portion and a plurality of leads each having an inner lead portion to be sealed with a molding member and an outer lead portion to protrude from the molding member, said inner lead portion having a first end providing an area for electrical connection with a semiconductor chip, said leads being discontinuous from one another in the vicinity of a boundary line between said inner and outer lead portions, said electrically insulating strip member being adhered to one surface of said leads and being extended along said boundary line between said inner and outer lead portions; bonding a semiconductor chip to said chip mounting portion of said lead frame, said semiconductor chip having a plurality of bonding pads formed on a main surface thereof; electrically connecting said plurality of bonding pads of said semiconductor chip with said first ends of said inner lead portions by wire bonding, said first ends of said leads and said semiconductor chip being spaced from each other; disposing said lead frame with said electrically insulating member and said semiconductor chip in a molding unit having an upper die and a lower die, said upper and lower dies having recessed areas which are of different sizes from each other and determine a size of a cavity of said molding unit, said size of said cavity being measured in a direction substantially perpendicular to a direction of a clamping motion of said dies, said lead frame with said electrically insulating member and said semiconductor chip being positioned such that said electrically insulating member is contacted with one of said upper and lower dies having a larger recessed area when said molding unit is closed and the other surface of said leads opposing to said one surface is contacted with the other of said upper and lower dies having a smaller recessed area and that an inner edge of said one of said upper and lower dies. corresponding to said boundary line, intersects said electrically insulating strip member, and said electrically insulating strip member has a first part inside said inner edge and a second part outside said inner edge, and a flat surface of the other of said upper and lower dies extends under said first part of said electrically insulating strip member; closing said molding unit to clamp said lead frame and thrusting parts of said second part of said electrically insulating strip member into spaces between adjacent leads of said leads, while said first part of said electrically insulating strip member remains on said one surface of said leads; and injecting a molding material into said cavity of said molding unit to form said molding member sealing said semiconductor chip and said inner lead portions of said leads.

Claim 2

A method of manufacturing a packaged semiconductor device comprising the steps of: providing a lead frame with an electrically insulating strip member, said lead frame having a chip mounting portion and a plurality of leads each having an inner lead portion to be sealed with a molding member and an outer lead portion to protrude from the molding member, said inner lead portion having a first end providing an area for electrical connection with a semiconductor chip, said leads being discontinuous from one another in the vicinity of a boundary line between said inner and outer lead portions, said electrically insulating strip member being adhered to one surface of said leads and being extended along said boundary line between said inner and outer lead portions; bonding a semiconductor chip to said chip mounting portion of said lead frame, said semiconductor chip having a plurality of bonding pads formed on a main surface thereof; electrically connecting said plurality of bonding pads of said semiconductor chip with said first ends of said inner lead portions by wire bonding, said first ends of said leads and said semiconductor chip being spaced from each other; disposing said lead frame with said electrically insulating member and said semiconductor chip in a molding unit having an upper die and a lower die, said upper and lower dies having recessed areas which are of different sizes from each other and determine a size of a cavity of said molding unit, said size of said cavity being measured in a direction substantially perpendicular to a direction of a clamping motion of said dies, said lead frame with said electrically insulating member and said semiconductor chip being positioned such that said electrically insulating member is contacted with one of said upper and lower dies having a larger recessed area when said molding unit is closed and the other surface of said leads opposing to said one surface is contacted with the other of said upper and lower dies having a smaller recessed area and that an inner edge of said one of said upper and lower dies. corresponding to said boundary line, intersects said electrically insulating strip member, and said electrically insulating strip member has a first part inside said inner edge and a second part outside said inner edge, and a flat surface of the other of said upper and lower dies extends under said first part of said electrically insulating strip member; closing said molding unit to clamp said lead frame and thrusting parts of said second part of said electrically insulating strip member into spaces between adjacent leads of said leads, while said first part of said electrically insulating strip member remains on said one surface of said leads; and injecting a molding material into said cavity of said molding unit to form said molding member sealing said semiconductor chip and said inner lead portions of said leads.

Claim 12

A method of manufacturing a packaged semiconductor device comprising the steps of: providing a lead frame with an electrically insulating strip member, said lead frame having a chip mounting portion and a plurality of leads surrounding said chip mounting portion, each of said plurality of leads having an inner lead portion to be sealed with a molding member and an outer lead portion to protrude from the molding member, said inner lead portion having a first end providing an area for electrical connection with a semiconductor chip, said leads being discontinuous from one another in the vicinity of a boundary line between said inner and outer lead portions, said electrically insulating strip member being adhered to one surface of said leads and being extended along said boundary line between said inner and outer lead portions; bonding a semiconductor chip to said chip mounting portion of said lead frame, said semiconductor chip having a plurality of bonding pads formed in a main surface thereof; electrically connecting said plurality of bonding pads of said semiconductor chip with the first ends of said inner lead portions by wire bonding, said first ends of said leads and said semiconductor chip being spaced from each other; disposing said lead frame with said electrically insulating strip member and said semiconductor chip in a molding unit having a first die and a second die, said first and second dies having recessed areas which are of different sizes from each other and determine a size of a cavity of said molding unit, said size of said cavity being measured in a first direction substantially perpendicular to a direction of a clamping motion of said first and second dies, each of said first and second dies having an upper flat surface for clamping said lead frame, and side and bottom surfaces for defining said recessed areas, said first die having a larger recessed area than that of said second die, said recessed area of said second die being positioned inside said recessed area of said first die in said first direction, said lead frame with said electrically insulating member and said semiconductor chip being positioned such that said electrically insulating strip member is contacted with said upper flat surface of said first die and the other surface of said leads opposing to said one surface is contacted with said upper flat surface of said second side and such that an inner edge of said first die, corresponding to said boundary line, intersects said electrically insulating strip member and said electrically insulating strip member has a first part inside said inner edge and a second part outside said inner edge, and said upper flat surface of said second die extends under said first part of said electrically insulating strip member; closing said molding unit to clamp said lead frame and thrusting parts of said second part of said electrically insulating strip member into spaces between adjacent leads of said leads, while said first part of said electrically insulating strip member being remained on said one surface of said leads; and injecting a molding material into said cavity of said molding unit to form said molding member sealing said semiconductor chip and said inner lead portions of said leads.

Claim 13

A method of manufacturing a packaged semiconductor device comprising the steps of: providing a lead frame with an electrically insulating strip member, said lead frame having a chip mounting portion and a plurality of leads surrounding said chip mounting portion, each of said plurality of leads having an inner lead portion to be sealed with a molding member and an outer lead portion to protrude from the molding member, said inner lead portion having a first end providing an area for electrical connection with a semiconductor chip, said leads being discontinuous from one another in the vicinity of a boundary line between said inner and outer lead portions, said electrically insulating strip member being adhered to one surface of said leads and being extended along said boundary line between said inner and outer lead portions; bonding a semiconductor chip to said chip mounting portion of said lead frame, said semiconductor chip having a plurality of bonding pads formed in a main surface thereof; electrically connecting said plurality of bonding pads of said semiconductor chip with the first ends of said inner lead portions by wire bonding, said first ends of said leads and said semiconductor chip being spaced from each other; disposing said lead frame with said electrically insulating strip member and said semiconductor chip in a molding unit having a first die and a second die, said first and second dies having recessed areas which are of different sizes from each other and determine a size of a cavity of said molding unit, said size of said cavity being measured in a first direction substantially perpendicular to a direction of a clamping motion of said first and second dies, each of said first and second dies having an upper flat surface for clamping said lead frame, and side and bottom surfaces for defining said recessed areas, said first die having a larger recessed area than that of said second die, said recessed area of said second die being positioned inside said recessed area of said first die in said first direction, said lead frame with said electrically insulating member and said semiconductor chip being positioned such that said electrically insulating strip member is contacted with said upper flat surface of said first die and the other surface of said leads opposing to said one surface is contacted with said upper flat surface of said second side and such that an inner edge of said first die, corresponding to said boundary line, intersects said electrically insulating strip member and said electrically insulating strip member has a first part inside said inner edge and a second part outside said inner edge, and said upper flat surface of said second die extends under said first part of said electrically insulating strip member; closing said molding unit to clamp said lead frame and thrusting parts of said second part of said electrically insulating strip member into spaces between adjacent leads of said leads, while said first part of said electrically insulating strip member being remained on said one surface of said leads; and injecting a molding material into said cavity of said molding unit to form said molding member sealing said semiconductor chip and said inner lead portions of said leads.