Patent US5882987A successfully refreshed from Google Patents.
US5882987A
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Smart-cut process for the production of thin semiconductor material films
Assignee: Soitec SA
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Filing: 1997-08-26
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Granted: 1999-03-16
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Expires: 2017-08-26
Abstract
Abstract A process applicable to the production of monocrystalline films improves on the Smart-Cut® process by using an etch stop layer in conjunction with the Smart-Cut® process. Because of the etch stop layer, no chemical-mechanical polishing (CMP) is required after fabrication. Thus, the thickness and smoothness of the device layer in the fabricated silicon on insulator (SOI) substrate is determined by the uniformity and smoothness of the deposited layers and wet etch selectivity, as opposed to the CMP parameters. Therefore, the smoothness and uniformity of the device layer are improved.
Inventors
- 👤 Kris V. Srikrishnan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 21:09
CPC Classifications
H; H10; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1914; H10P90/1916; H10W; H10W10/00; H10W10/10; H10W10/181; Y; Y10; Y10S; Y10S148/00; Y10S148/05; Y10S438/00; Y10S438/977
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
145 words
A method of forming a thin semiconductor layer of substantially uniform thickness upon which semiconductor structures can be subsequently formed, comprising the steps of: providing a first wafer comprising a semiconductor substrate; forming an etch stop layer having a thickness upon said first wafer; forming a device layer having a thickness on said etch stop layer;. forming a bonding layer on said device layer; implanting ions into said semiconductor substrate to form a buried layer therein; bonding said bonding layer to a second wafer; heating said bonded first and second wafers to a first temperature; separating said bonded first and second wafers along said buried layer so that said second wafer has a top surface layer; and removing said top surface layer and said etch stop layer, whereby underlying portions of said device layer remain on said second wafer to form the thin semiconductor layer.
Claim 2
Independent Claim
145 words
A method of forming a thin semiconductor layer of substantially uniform thickness upon which semiconductor structures can be subsequently formed, comprising the steps of: providing a first wafer comprising a semiconductor substrate; forming an etch stop layer having a thickness upon said first wafer; forming a device layer having a thickness on said etch stop layer;. forming a bonding layer on said device layer; implanting ions into said semiconductor substrate to form a buried layer therein; bonding said bonding layer to a second wafer; heating said bonded first and second wafers to a first temperature; separating said bonded first and second wafers along said buried layer so that said second wafer has a top surface layer; and removing said top surface layer and said etch stop layer, whereby underlying portions of said device layer remain on said second wafer to form the thin semiconductor layer.
Claim 3
Dependent Claim
29 words
The method according to claim 1, further comprising the step of heating said second wafer having said top surface layer to a second temperature after said step of separating.
Claim 4
Dependent Claim
33 words
The method of claim 2, wherein said step of heating the second wafer includes annealing at about 1000° C. for a time in the range between about 30 minutes and about 8 hours.
Claim 5
Dependent Claim
32 words
The method according to claim 1, wherein said semiconductor substrate is a silicon (Si) substrate and said ions comprise hydrogen ions, such that said buried layer is comprised of hydrogen and silicon.
Claim 6
Dependent Claim
38 words
The method according to claim 4, wherein said hydrogen ions are implanted at a dose in the range between about 10 16 and 2×10 17 ions/cm 2 with an energy in the range between 50 and 150 KeV.
Claim 7
Dependent Claim
28 words
The method according to claim 1, wherein said buried layer is formed at a depth between 1 and 2 μm beneath a top surface of said bonding layer.
Claim 8
Dependent Claim
34 words
The method according to claim 1, wherein said step of heating includes annealing at a range between about 400° and 600° C., for a time in the range between about 30 and 120 minutes.
Claim 9
Dependent Claim
21 words
The method according to claim 1, wherein said step of bonding said bonding layer to said second wafer comprises hydrophilic bonding.
Claim 10
Dependent Claim
80 words
The method according to claim 1, wherein wherein said semiconductor substrate is a Si substrate and said step of bonding said bonding layer to said second wafer comprises the steps of: forming a layer of silicon dioxide on an exposed surface of said second wafer; wetting said bonding layer and said silicon dioxide layer; bringing said bonding layer and said silicon dioxide layer into contact; and compressing said bonding layer and said silicon dioxide layer to form a bond therebetween.
Claim 11
Dependent Claim
64 words
The method according to claim 1, wherein said step of removing the top surface layer and said etch stop layer comprises the steps of: etching the top surface layer in a first etchant which does not appreciably attack said etch stop layer; and etching said etch stop layer in a second etchant which does not appreciably attack a remaining part of said device layer.
Claim 12
Dependent Claim
21 words
The method according to claim 10, wherein said first etchant comprises a solution of one of potassium hydroxide and ammonium hydroxide.
Claim 13
Dependent Claim
53 words
The method according to claim 1, wherein said step of removing said top surface layer and said etch stop layer comprises removing said top surface layer with a low-selectivity etch having a selectivity of 10:1 or below, followed by removing said etch stop layer with a low selectivity etch of 10:1 or below.
Claim 14
Dependent Claim
45 words
The method according to claim 1, wherein said semiconductor substrate is a Si substrate and said etch stop layer comprises one of a high doped Si layer, a silicon-germanium (Si-Ge) layer, a strained Si-Ge layer, a Ge layer, and a Ge compensated layer of Si-Ge.
Claim 15
Dependent Claim
30 words
The method according to claim 1, wherein said etch stop layer is doped with boron at a concentration in the range between 10 20 and 10 21 atoms/cm 3 .
Claim 16
Dependent Claim
23 words
The method according to claim 1, wherein the thickness of said etch stop layer is in the range between 100 and 2000 Å.
Claim 17
Dependent Claim
17 words
The method according to claim 15, wherein the thickness of said etch stop layer is 250 Å.
Claim 18
Dependent Claim
19 words
The method according to claim 1, wherein said step of forming said etch stop layer uses chemical vapor deposition.
Claim 19
Dependent Claim
25 words
The method according to claim 1, wherein said semiconductor substrate is a Si substrate and said device layer is one of Si, Ge, and Si-Ge.
Claim 20
Dependent Claim
26 words
The method according to claim 18, wherein said device layer is Si-Ge having an atomic percentage of Ge in the range between 5 and 30 percent.
Claim 21
Dependent Claim
27 words
The method according to claim 1, wherein said semiconductor substrate is a Si substrate and said device layer comprises at least one of Si, Ge, and Si-Ge.
Claim 22
Dependent Claim
22 words
The method according to claim 1, wherein the thickness of the device layer is in the range between 500 and 5000 Å.
Claim 23
Dependent Claim
16 words
The method according to claim 21, wherein the thickness of said device layer is 1000 Å.
Claim 24
Dependent Claim
32 words
The method according to claim 1, further comprising the steps of photolithographically patterning and etching said bonding layer and said device layer to form apertures therein prior to said step of bonding.
Claim 25
Dependent Claim
12 words
The method according to claim 1, wherein the semiconductor substrate comprises silicon.
Claim 26
Independent Claim
227 words
A method for forming a thin silicon on insulator structure, comprising: providing a first wafer comprising a silicon substrate; forming an etch stop layer having a thickness upon said first wafer; forming a device layer having a thickness on said etch stop layer; forming a bonding layer on said device layer; implanting hydrogen ions into said silicon substrate to form a buried hydrogen-rich layer therein; forming a layer of silicon dioxide on an exposed surface of a second wafer; wetting said bonding layer and said silicon dioxide layer; bringing said bonding layer and said silicon dioxide layer into contact; compressing said bonding layer and said silicon dioxide layer to form a hydrophilic bond therebetween; annealing said bonded first and second wafers at a first temperature; separating said bonded wafers along said buried hydrogen-rich layer so that said second wafer has a top surface layer comprising Si from said first wafer; annealing said second wafer having said top surface layer to a second temperature; etching said top surface layer in a first etchant which does not appreciably attack a remaining part of said etch stop layer; and etching said etch stop layer in a second etchant which does not appreciably attack a remaining part of said device layer; whereby underlying portions of said device layer remain on the second wafer to form the thin silicon on insulator structure.
Claim 27
Independent Claim
227 words
A method for forming a thin silicon on insulator structure, comprising: providing a first wafer comprising a silicon substrate; forming an etch stop layer having a thickness upon said first wafer; forming a device layer having a thickness on said etch stop layer; forming a bonding layer on said device layer; implanting hydrogen ions into said silicon substrate to form a buried hydrogen-rich layer therein; forming a layer of silicon dioxide on an exposed surface of a second wafer; wetting said bonding layer and said silicon dioxide layer; bringing said bonding layer and said silicon dioxide layer into contact; compressing said bonding layer and said silicon dioxide layer to form a hydrophilic bond therebetween; annealing said bonded first and second wafers at a first temperature; separating said bonded wafers along said buried hydrogen-rich layer so that said second wafer has a top surface layer comprising Si from said first wafer; annealing said second wafer having said top surface layer to a second temperature; etching said top surface layer in a first etchant which does not appreciably attack a remaining part of said etch stop layer; and etching said etch stop layer in a second etchant which does not appreciably attack a remaining part of said device layer; whereby underlying portions of said device layer remain on the second wafer to form the thin silicon on insulator structure.
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