Semiconductor integrated circuit

Claim 2

A semiconductor integrated circuit comprising: a controlled circuit having a plurality of memory cells, each of said plurality of memory cells comprising a MOSFET having a gate electrode; an internal boosted power supply node for boosting a signal input to a word line, said word line coupled to the gate electrode of the MOSFET of each of the plurality of memory cells; and a boosted power supply generating circuit for supplying charge to the internal boosted power supply node upon receipt of an external signal having an operation mode directing the controlled circuit to operate and a stand-by mode directing the controlled circuit to stand-by; wherein said boosted power supply generating circuit comprises: at least one main boosted power supply generating circuit coupled to the internal boosted power supply node, for synchronously operating with the external signal, when the external signal is switched from a stand-by mode to an operation mode, to supply a predetermined amount of charge to the internal boosted power supply node; an oscillating circuit for generating a first oscillating signal having a first frequency and a second oscillating signal having a second frequency which is higher than said first frequency; a sub-boosted power supply generating circuit coupled to an output of the oscillating circuit and the internal boosted power supply node, said sub-boosted power supply generating circuit operative for generating a first charge level and a second charge level, said first charge level being larger than said second charge level, said first charge level and said second charge level corresponding to said first oscillating signal and said second oscillating signal, respectively; and charge supply capability control means for controlling the sub-boosted power supply generating circuit upon receipt of the external signal so that the sub-boosted power supply generating circuit continuously supplies the first charge level to the internal boosted power supply node when the external signal is in said operating mode, and continuously supplies the second charge level to the internal boosted power supply node when the external signal is in said stand-by mode.

Claim 3

The semiconductor integrated circuit of claim 1, wherein said charge supply capability control means comprises a frequency switching circuit for controlling said oscillating circuit upon receipt of said external signal so as to generate said oscillating signal having the first frequency when said external signal is in operation mode and said oscillating signal having the second frequency when said external signal is in standby mode.

Claim 4

The semiconductor integrated circuit of claim 2, wherein said oscillating circuit comprises a first oscillating circuit for generating said oscillating signal having said first frequency and a second oscillating circuit for generating said oscillating signal having said second frequency which is higher than said first frequency, and said charge supply capability control means comprises said frequency switching circuit for performing switching upon receipt of said external signal so as to input, to said sub-boosted power supply generating circuit, the oscillating signal of said first oscillating circuit when said external signal is in operation mode and the oscillating signal of said second oscillating circuit when said external signal is in standby mode.

Claim 5

The semiconductor integrated circuit of claim 1, wherein said sub-boosted power supply generating circuit comprises a plurality of sub-boosted power supply generating circuits in which capacitors for supplying charges to said internal boosted power supply node are provided and have different capacities, and said charge supply capability control means is a switching circuit which performs switching upon receipt of said external signal so as to boost said internal boosted power supply node by the sub-boosted power supply generating circuit in which the capacitor having the small capacitance is provided when the external signal is in the standby mode, and by the sub-boosted power supply generating circuit in which the capacitor having the great capacitance is provided when the external signal is in the operation mode.

Claim 6

The semiconductor integrated circuit of claim 1, wherein said controlled circuit is either a volatile memory such as a DRAM or a non-volatile memory such as an EEPROM or a ferroelectric memory, and said external signal is inputted to said gate electrode of the memory cells of said memory.

Claim 7

The semiconductor integrated circuit of claim 1, further comprising potential limiting means for limiting the potential of said internal boosted power supply node to a set level or less by drawing the charges of said internal boosted power supply node after the potential of said external signal is raised.

Claim 8

A semiconductor integrated circuit comprising: a controlled circuit having a plurality of memory cells, each of said plurality of memory cells comprising a MOSFET having a gate electrode; an internal boosted power supply node for boosting a signal input to a word line, said word line coupled to the gate electrode of the MOSFET of each of the plurality of memory cells; and a boosted power supply generating circuit for supplying charge to the internal boosted power supply node upon receipt of an external signal having an operation mode directing the controlled circuit to operate and a stand-by mode directing the controlled circuit to stand-by; wherein said boosted power supply generating circuit comprises: at least one main boosted power supply generating circuit for synchronously operating with the external signal, when the external signal is switched from a stand-by mode to an operation mode, to supply a predetermined amount of charge to the internal boosted power supply node; an oscillating circuit for generating a first oscillating signal having a first frequency and a second oscillating signal having a second frequency which is higher than said first frequency; a sub-boosted power supply generating circuit coupled to an output of the oscillating circuit and the internal boosted power supply node, said sub-boosted power supply generating circuit comprising a single charge pump and operative for generating a first charge level and a second charge level, said first charge level being larger than said second charge level, said first charge level and said second charge level corresponding to said first oscillating signal and said second oscillating signal, respectively; a level detecting circuit for detecting the voltage level of the internal boosted power supply node; and charge supply capability control means for controlling the sub-boosted power supply generating circuit upon receipt of a signal output from the level detecting circuit so that the sub-boosted power supply generating circuit supplies the first charge level to the internal boosted power supply node when the level detected by the level detecting circuit is lower than a first set value, and supplies the second charge level to the internal boosted power supply node when the level detected by the level detecting circuit is higher than the first set value.

Claim 9

A semiconductor integrated circuit comprising: a controlled circuit having a plurality of memory cells, each of said plurality of memory cells comprising a MOSFET having a gate electrode; an internal boosted power supply node for boosting a signal input to a word line, said word line coupled to the gate electrode of the MOSFET of each of the plurality of memory cells; and a boosted power supply generating circuit for supplying charge to the internal boosted power supply node upon receipt of an external signal having an operation mode directing the controlled circuit to operate and a stand-by mode directing the controlled circuit to stand-by; wherein said boosted power supply generating circuit comprises: at least one main boosted power supply generating circuit for synchronously operating with the external signal, when the external signal is switched from a stand-by mode to an operation mode, to supply a predetermined amount of charge to the internal boosted power supply node; an oscillating circuit for generating a first oscillating signal having a first frequency and a second oscillating signal having a second frequency which is higher than said first frequency; a sub-boosted power supply generating circuit coupled to an output of the oscillating circuit and the internal boosted power supply node, said sub-boosted power supply generating circuit comprising a single charge pump and operative for generating a first charge level and a second charge level, said first charge level being larger than said second charge level, said first charge level and said second charge level corresponding to said first oscillating signal and said second oscillating signal, respectively; a level detecting circuit for detecting the voltage level of the internal boosted power supply node; and charge supply capability control means for controlling the sub-boosted power supply generating circuit upon receipt of a signal output from the level detecting circuit so that the sub-boosted power supply generating circuit supplies the first charge level to the internal boosted power supply node when the level detected by the level detecting circuit is lower than a first set value, and supplies the second charge level to the internal boosted power supply node when the level detected by the level detecting circuit is higher than the first set value.

Claim 10

The semiconductor integrated circuit of claim 7, wherein said level detecting circuit comprises a first level detecting circuit for detecting that the voltage level of the internal boosted power supply node is lower than said first set value, and a second level detecting circuit for detecting that the voltage level of the internal boosted power supply node is higher than said first set value, and said charge supply capability control means performs switching on receipt of outputs of said level detecting circuits so as to the supply said second charge level when the voltage level of said internal boosted power supply node is higher than said first set value and to supply said first charge level when the voltage level of said internal boosted power supply node is lower than said first set value.

Claim 11

The semiconductor integrated circuit of claim 7, wherein said charge supply capability control means comprises a frequency switching circuit for controlling said oscillating circuit upon receipt of a detection signal of said level detecting circuit so as to generate said oscillating signal having the first frequency when the voltage level of said internal boosted power supply node is lower than said first set value, and said oscillating signal having the second frequency when the voltage level of said internal boosted power supply node is higher than said first set value.

Claim 12

The semiconductor integrated circuit of claim 9, wherein said oscillating circuit comprises a first oscillating circuit for generating said oscillating signal having said first frequency and a second oscillating circuit for generating said oscillating signal having said second frequency which is higher than said first frequency, and said charge supply capability control means comprises the frequency switching circuit for performing switching upon receipt of the detection signal of said level detecting circuit so as to input, to said sub-boosted power supply generating circuit, the oscillating signal of said first oscillating circuit when the voltage level of said internal boosted power supply node is lower than said first set value, and the oscillating signal of said second oscillating circuit when the voltage level of said internal boosted power supply node is hither than said first set value.

Claim 13

The semiconductor integrated circuit of claim 7, wherein said sub-boosted power supply generating circuit comprises a plurality of sub-boosted power supply generating circuits in which capacitors for supplying charges to said internal boosted power supply node are provided and have different capacities, and said charge supply capability control means is a switching circuit which performs switching upon receipt of the detection signal of said level detecting circuit so as to boost said internal boosted power supply node by the sub-boosted power supply generating circuit in which the capacitor having the small capacitance is provided when the voltage level of said internal boosted power supply node is higher than said first value, and by the sub-boosted power supply generating circuit in which the capacitor having the great capacitance is provided when the voltage level of said internal boosted power supply node is lower than said first set value.

Claim 14

The semiconductor integrated circuit of claim 7, wherein said controlled circuit is either a volatile memory such as a DRAM or a non-volatile memory such as an EEPROM or a ferroelectric memory, and said external signal is inputted to said gate electrode of the memory cells of said memory.

Claim 15

The semiconductor integrated circuit of claim 7, further comprising potential limiting means for limiting the potential of said internal boosted power supply node to a set level or less by drawing the charges of said internal boosted power supply node after the potential of said external signal is raised.

Claim 16

A semiconductor integrated circuit comprising; a controlled circuit having a plurality of active elements, an internal boosted power supply node connected to said active elements, and a boosted power supply generating circuit for supplying charges to said internal boosted power supply node on receipt of an external signal which directs said active elements of said controlled circuit to operate or stand by, wherein said boosted power supply generating circuit comprises; at least one main boosted power supply generating circuit which operates synchronously with said external signal to supply a predetermined amount of charge to said internal boosted power supply node when said external signal is in operation mode, an oscillating circuit for generating an oscillating signal, a sub-boosted power supply generating circuit for supplying an amount of charge corresponding to the frequency of an oscillating signal generated by said oscillating circuit on receipt of the oscillating signal, and potential limiting means for drawing the charges of said internal boosted power supply node so as to limit the potential of said internal boosted power supply node to the set level or less after a word line coupled to said active elements in said controlled circuit rises.

Claim 17

A semiconductor integrated circuit comprising; a controlled circuit having a plurality of active elements, an internal boosted power supply node connected to said active elements, and a boosted power supply generating circuit for supplying charges to said internal boosted power supply node on receipt of an external signal which directs said active elements of said controlled circuit to operate or stand by, wherein said boosted power supply generating circuit comprises; at least one main boosted power supply generating circuit which operates synchronously with said external signal to supply a predetermined amount of charge to said internal boosted power supply node when said external signal is in operation mode, an oscillating circuit for generating an oscillating signal, a sub-boosted power supply generating circuit for supplying an amount of charge corresponding to the frequency of an oscillating signal generated by said oscillating circuit on receipt of the oscillating signal, and potential limiting means for drawing the charges of said internal boosted power supply node so as to limit the potential of said internal boosted power supply node to the set level or less after a word line coupled to said active elements in said controlled circuit rises.

Claim 18

The semiconductor integrated circuit of claim 14, wherein said potential limiting means comprises; a potential limiting circuit having an output coupled to said internal boosted power supply node, said potential limiting circuit operative for drawing the charges of said internal boosted power supply node on receipt of the external signal in operation mode, and a control circuit for performing control so as to input the external signal in the operation mode to said potential limiting circuit after a time for which said external signal is changed from the standby mode to the operation mode and said internal boosted power supply node is lowered by power consumption by said active element of said controlled circuit portion.

Claim 19

A semiconductor integrated circuit comprising; a controlled circuit having a plurality of active elements, an internal boosted power supply node connected to said active elements to boost a signal inputted to said active elements, and a boosted power supply generating circuit for supplying charges to said internal boosted power supply node on receipt of an external signal which directs data fetch from said controlled circuit, wherein said boosted power supply generating circuit comprises; a control circuit for outputting an output determination signal for determining the output operation of the data from said controlled circuit in response to said external signal, an output circuit having a transistor controlled by said internal boosted power supply node for outputting the output data on receipt of the output determination signal from said control circuit, and a main boosted power supply generating circuit having the output connected to said internal boosted power supply node and said output circuit for supplying charges to the gate of said transistor of said output circuit and said internal boosted power supply node on receipt of an enable signal of said control circuit.

Claim 20

A semiconductor integrated circuit comprising; a controlled circuit having a plurality of active elements, an internal boosted power supply node connected to said active elements to boost a signal inputted to said active elements, and a boosted power supply generating circuit for supplying charges to said internal boosted power supply node on receipt of an external signal which directs data fetch from said controlled circuit, wherein said boosted power supply generating circuit comprises; a control circuit for outputting an output determination signal for determining the output operation of the data from said controlled circuit in response to said external signal, an output circuit having a transistor controlled by said internal boosted power supply node for outputting the output data on receipt of the output determination signal from said control circuit, and a main boosted power supply generating circuit having the output connected to said internal boosted power supply node and said output circuit for supplying charges to the gate of said transistor of said output circuit and said internal boosted power supply node on receipt of an enable signal of said control circuit.

Claim 21

The semiconductor integrated circuit of claim 16, wherein said boosted power supply generating circuit operates synchronously with the fall of a column address strobe signal (XCAS) or an output enable signal (XOE) from the "H" level to the "L" level, and supplies charges to said internal boosted power supply node.

Claim 22

The semiconductor integrated circuit of claim 16, wherein said boosted power supply generating circuit operates synchronously with the fall of XCAS and XOE from the "H" level to the "L" level when a write enable signal (XWE) has the "H" level, and supplies charges to said internal boosted power supply node.

Claim 23

The semiconductor integrated circuit of claim 16, wherein said boosted power supply generating circuit supplies charges to said internal boosted power supply node only when outputting High data.