US5434820A
Expired / Lapsed
US
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Back bias voltage generator circuit of a semiconductor memory device
Assignee: SK Hynix Inc
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Filing: 1993-10-08
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Granted: 1995-07-18
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Expires: 2013-10-08
Abstract
Abstract A Vbb generator having several distributed Vbb generators, which are located respectively adjacent to memory array blocks is disclosed. The distributed Vbb generator is activated during the time when a memory block located adjacent the Vbb generator is accessed for write/read operations. The back bias voltage generator circuit has a first Vbb generator and a second Vbb generator for supplying a back bias voltage to the substrate. The second Vbb generator comprises an oscillator for generating a clock pulse and a plurality of distributed Vbb generators. The distributed Vbb generators include an auxiliary pumping portion including a buffer portion for buffering the clock pulse from the oscillator, a pumping capacitor connected to the output of the buffer portion for pumping a back bias voltage, and a rectifying portion connected to the pumping capacitor for supplying the back bias voltage to the substrate, and a switch for connecting the clock pulse from the oscillator to the auxiliary pumping portion, the clock pulse activating a pumping operation of the auxiliary pumping portion.
Inventors
- 👤 Tae-hoon Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 03:44
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C5/00; G11C5/14; G11C5/145; G11C5/146
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
105 words
A back bias voltage generator circuit of a semiconductor memory device having a first Vbb generator and a second Vbb generator for supplying a back bias voltage to a substrate, the memory device having memory cell array blocks controlled by memory cell array block selecting signals, wherein the second Vbb generator comprises: an oscillator for generating a clock pulse; and a plurality of distributed Vbb generators, the distributed Vbb generators being located respectively adjacent to memory cell array blocks and receiving a clock pulse from the oscillator, the distributed Vbb generators being activated in accordance with one or more memory cell array block selecting signals.
Claim 2
Dependent Claim
105 words
A back bias voltage generator circuit of a semiconductor memory device having a first Vbb generator and a second Vbb generator for supplying a back bias voltage to a substrate, the memory device having memory cell array blocks controlled by memory cell array block selecting signals, wherein the second Vbb generator comprises: an oscillator for generating a clock pulse; and a plurality of distributed Vbb generators, the distributed Vbb generators being located respectively adjacent to memory cell array blocks and receiving a clock pulse from the oscillator, the distributed Vbb generators being activated in accordance with one or more memory cell array block selecting signals.
Claim 3
Dependent Claim
104 words
A back bias voltage generator circuit of a semiconductor memory device as claimed in claim 1, wherein the distributed Vbb generators comprise: an auxiliary pumping portion including a buffer portion for buffering the clock pulse received from the oscillator, a pumping capacitor connected to the output of the buffer portion for pumping a back bias voltage, and a rectifying portion connected to the pumping capacitor for supplying the back bias voltage to the substrate; and a switching means for selectably connecting the clock pulse from the oscillator to the auxiliary pumping portion, the clock pulse activating a pumping operation of the auxiliary pumping portion.
Claim 4
Dependent Claim
27 words
A back bias voltage generator circuit of a semiconductor memory device as claimed in claim 1, wherein the oscillator is activated by a row address strobe signal.
Claim 5
Dependent Claim
23 words
A back bias voltage generator circuit of a semiconductor memory device as claimed in claim 2, wherein the switching means is a MOSFET.
Claim 6
Dependent Claim
24 words
A back bias voltage generator circuit of a semiconductor memory device as claimed in claim 2, wherein the switching means is an n-channel MOSFET.
Claim 7
Dependent Claim
25 words
A back bias voltage generator circuit of a semiconductor memory device as claimed in claim 2, wherein the buffer portion comprises one or more invertors.
Claim 8
Dependent Claim
25 words
A back bias voltage generator circuit of a semiconductor memory device as claimed in claim 2, wherein the rectifying portion comprises at least two diodes.
Claim 9
Dependent Claim
28 words
A back bias voltage generator circuit of a semiconductor memory device as claimed in claim 1, wherein the distributed Vbb generators are located between memory cell array blocks.
Claim 10
Dependent Claim
33 words
A back bias voltage generator circuit of a semiconductor memory device as claimed in claim 8, wherein the distributed Vbb generators are located beside row decoders respectively positioned between memory cell array blocks.
Claim 11
Dependent Claim
106 words
A semiconductor memory device comprising: a plurality of memory cell arrays formed on a substrate; a first back bias voltage generating circuit for applying a back bias voltage to the substrate; means for receiving memory array selecting signals, the memory array selecting signals causing the memory device to operate selected memory cell arrays; an oscillator for generating clock pulses; a plurality of second back bias voltage generating circuits for applying a back bias voltage to the substrate, the second back bias voltage generating circuits being positioned correspondingly with the memory cell arrays and activated in response to one or more of the memory array selecting signals.
Claim 12
Dependent Claim
106 words
A semiconductor memory device comprising: a plurality of memory cell arrays formed on a substrate; a first back bias voltage generating circuit for applying a back bias voltage to the substrate; means for receiving memory array selecting signals, the memory array selecting signals causing the memory device to operate selected memory cell arrays; an oscillator for generating clock pulses; a plurality of second back bias voltage generating circuits for applying a back bias voltage to the substrate, the second back bias voltage generating circuits being positioned correspondingly with the memory cell arrays and activated in response to one or more of the memory array selecting signals.
Claim 13
Dependent Claim
22 words
A semiconductor memory device as claimed in claim 10, wherein the second back bias generating circuits are located between memory cell arrays.
Claim 14
Dependent Claim
37 words
A semiconductor memory device as claimed in claim 10, further comprising row decoders coupled to the memory cell arrays, wherein the second back bias generating circuits are located beside row decoders respectively positioned between memory cell arrays.
Claim 15
Independent Claim
141 words
A method for generating back bias voltages in a semiconductor memory device formed in a substrate and having a plurality of memory cell arrays selected by memory cell array selecting signals, comprising: generating a first memory cell array selecting signal for selecting a first memory cell array; activating a first back bias generating circuit positioned correspondingly to the first memory cell array in accordance with the first memory cell array selecting signal, the first back bias generating circuit providing a back bias voltage to the substrate; generating a second memory cell array selecting signal for selecting a second memory cell array; and activating a second back bias generating circuit positioned correspondingly to the second memory cell array in accordance with the second memory cell array selecting signal, the second back bias generating circuit providing a back bias voltage to the substrate.
Claim 16
Independent Claim
141 words
A method for generating back bias voltages in a semiconductor memory device formed in a substrate and having a plurality of memory cell arrays selected by memory cell array selecting signals, comprising: generating a first memory cell array selecting signal for selecting a first memory cell array; activating a first back bias generating circuit positioned correspondingly to the first memory cell array in accordance with the first memory cell array selecting signal, the first back bias generating circuit providing a back bias voltage to the substrate; generating a second memory cell array selecting signal for selecting a second memory cell array; and activating a second back bias generating circuit positioned correspondingly to the second memory cell array in accordance with the second memory cell array selecting signal, the second back bias generating circuit providing a back bias voltage to the substrate.
Claim 17
Dependent Claim
46 words
The method of claim 13, further comprising: detecting whether the substrate back bias voltage has exceeded a predetermined threshold voltage level; and selectively activating a third back bias voltage generating circuit depending upon whether the substrate back bias voltage has exceeded the predetermined threshold voltage level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-17 | 1999-01-16 | 1999-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-17 | 2003-01-16 | 2003-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-17 | 2007-01-16 | 2007-07-18 | $7700.00 | Window Closed / Lapsed |