Substrate bias generation circuit used in semiconductor integrated circuit

Claim 2

A MOS memory device comprising: a semiconductor substrate; a MOS memory integrated circuit for storing data formed on said semiconductor substrate; and a plurality of substrate bias voltage generating circuits for generating substrate bias volt ages to apply a desired potential to said semiconductor substrate and for absorbing surplus carries which are injected into said semiconductor substrate from said MOS memory integrated circuit, said substrate bias voltage generating circuits being arranged so as to minimize fluctuations of the desired substrate potential due to surplus carriers injected into said substrate from said MOS integrated circuit.

Claim 3

A MOS memory device according to claim 1, wherein said semiconductor integrated circuit includes CMOS memory cells.

Claim 4

A MOS memory device according to claim 1, wherein said semiconductor integrated circuit includes CMOS inverters.

Claim 5

A MOS memory device according to claim 1, wherein said plurality of substrate bias voltage generation circuits are arranged to be allocated two divided substantially equal areas of said semiconductor integrated circuit.

Claim 6

A MOS memory device according to claim 1, wherein at least one of said plurality of substrate bias generation circuits is arranged near an area of said semiconductor integrated circuit in which current is relatively concentrated.

Claim 7

A MOS memory device according to claim 1, wherein said plurality of substrate bias voltage generating circuits each comprise a ring oscillator having an output, first and second diodes having respective anodes and cathodes, and a capacitor having first and second terminals, the first terminal of said capacitor being connected to the output of said ring oscillator, the cathode of said first diode being connected to the second terminal of said capacitor, the anode of said second diode being connected to the second terminal of said capacitor, the anode of said first diode being connected to said semiconductor substrate, and the cathode of said second diode being connected to a ground of said semiconductor integrated circuit.

Claim 8

A MOS memory device according to claim 1, wherein said substrate bias voltage generating circuits are positioned such that a distance from a first bias voltage generating circuit to a portion of said semiconductor integrated circuit furthest from said first bias voltage generating circuit is substantially equal to a distance from a second bias voltage generating circuit to a portion of said semiconductor integrated circuit further from said second bias voltage generating circuit.

Claim 9

A MOS memory device comprising: a semiconductor substrate; a MOS memory integrated circuit for storing data formed in said semiconductor substrate; and a substrate bias voltage generating circuit for generating a a substrate bias voltage to apply a desired potential to said semiconductor substrate and for absorbing surplus carriers which are injected into said semiconductor substrate from said MOS memory integrated circuit, said substrate bias voltage generating circuit being arranged substantially at a central portion of said MOS memory integrated circuit.

Claim 10

A MOS memory device comprising: a semiconductor substrate; a MOS memory integrated circuit for storing data formed in said semiconductor substrate; and a substrate bias voltage generating circuit for generating a a substrate bias voltage to apply a desired potential to said semiconductor substrate and for absorbing surplus carriers which are injected into said semiconductor substrate from said MOS memory integrated circuit, said substrate bias voltage generating circuit being arranged substantially at a central portion of said MOS memory integrated circuit.

Claim 11

A MOS memory device comprising: a semiconductor substrate having a first conductivity type; semiconductor well areas having a second conductivity type formed in a surface region of said semiconductor substrate; a MOS memory integrated circuit including CMOS transistors formed in said semiconductor well areas and said semiconductor substrate, and a plurality of substrate bias voltage generating circuits for generating substrate bias voltages to apply a desired potential to said semiconductor substrate and said semiconductor well areas and for absorbing surplus carriers which are injected into said semiconductor well areas from said MOS memory integrated circuit, said bias voltage generating circuits being arranged so as to minimize fluctuation of the desired potential due to the surplus carriers injected into said semiconductor substrate from said MOS memory integrated circuit.

Claim 12

A MOS memory device comprising: a semiconductor substrate having a first conductivity type; semiconductor well areas having a second conductivity type formed in a surface region of said semiconductor substrate; a MOS memory integrated circuit including CMOS transistors formed in said semiconductor well areas and said semiconductor substrate, and a plurality of substrate bias voltage generating circuits for generating substrate bias voltages to apply a desired potential to said semiconductor substrate and said semiconductor well areas and for absorbing surplus carriers which are injected into said semiconductor well areas from said MOS memory integrated circuit, said bias voltage generating circuits being arranged so as to minimize fluctuation of the desired potential due to the surplus carriers injected into said semiconductor substrate from said MOS memory integrated circuit.

Claim 13

A MOS memory device device according to claim 9, wherein said semiconductor integrated circuit includes CMOS memory cells.

Claim 14

A CMOS memory device device according to claim 9, wherein said semiconductor integrated circuit includes CMOS inverters.

Claim 15

A MOS memory device device according to claim 9, wherein said plurality of substrate bias voltage generation circuits are arranged to be allocated two divided substantially equal areas of said semiconductor integrated circuit.

Claim 16

A MOS memory device device according to claim 9, wherein at least one of said plurality of substrate bias generation circuits is arranged near that area of said semiconductor integrated circuit in which current is relatively concentrated.

Claim 17

A MOS memory device according to claim 9, wherein said plurality of substrate bias voltage generating circuits each comprise a ring oscillator having an output, first and second diodes having respective anodes and cathodes, and a capacitor having first and second terminals, the first terminal of said capacitor being connected to the output of said ring oscillator, the cathode of said first diode being connected to the second terminal of said capacitor, the anode of said second diode being connected to the second terminal of said capacitor, the anode of said first diode being connected to said semiconductor substrate, and the cathode of said second diode being connected to a ground of said semiconductor integrated circuit.

Claim 18

A MOS memory device according to claim 9, wherein said substrate bias voltage generating circuits are positioned such that a distance from a first bias voltage generating circuit to a portion of said semiconductor integrated circuit furthest from said first bias voltage generating circuit is substantially equal to a distance from a second bias voltage generating circuit to a portion of said semiconductor integrated circuit furthest from said second bias voltage generating circuit.

Claim 19

A MOS memory device comprising: a semiconductor substrate having a first conductivity type; semiconductor well areas having a second conductivity type formed in a surface region of said semiconductor substrate; a MOS memory integrated circuit including CMOS transistors formed in said semiconductor well areas and said semiconductor substrate; and a substrate bias voltage generating circuit for generating a substrate bias voltage to apply a desired potential to said semiconductor well areas and said semiconductor substrate and for absorbing surplus carriers which are injected into said semiconductor well areas due to operation of said MOS memory integrated circuit, said bias voltage generating circuit being arranged at substantially a central portion of said MOS memory integrated circuit.

Claim 20

A MOS memory device comprising: a semiconductor substrate having a first conductivity type; semiconductor well areas having a second conductivity type formed in a surface region of said semiconductor substrate; a MOS memory integrated circuit including CMOS transistors formed in said semiconductor well areas and said semiconductor substrate; and a substrate bias voltage generating circuit for generating a substrate bias voltage to apply a desired potential to said semiconductor well areas and said semiconductor substrate and for absorbing surplus carriers which are injected into said semiconductor well areas due to operation of said MOS memory integrated circuit, said bias voltage generating circuit being arranged at substantially a central portion of said MOS memory integrated circuit.

Claim 21

A semiconductor integrated circuit comprising: a semiconductor substrate having an internal resistance and capacitance; a semiconductor integrated circuit formed on said semiconductor substrate; and a plurality of substrate bias voltage generating circuits positioned on said semiconductor substrate and generating substrate bias voltages for applying a desired potential to said semiconductor substrate, said substrate bias voltage generating circuits being positioned to minimize a time constant of said semiconductor substrate determined by the internal resistance and capacitance of said semiconductor substrate such that a time from when surplus carriers are injected into said substrate form said semiconductor integrated circuit until said surplus carriers are absorbed by one of said substrate bias voltage voltage generating circuits is substantially minimized, thereby reducing fluctuation of the desired potential.

Claim 22

A semiconductor integrated circuit comprising: a semiconductor substrate having an internal resistance and capacitance; a semiconductor integrated circuit formed on said semiconductor substrate; and a plurality of substrate bias voltage generating circuits positioned on said semiconductor substrate and generating substrate bias voltages for applying a desired potential to said semiconductor substrate, said substrate bias voltage generating circuits being positioned to minimize a time constant of said semiconductor substrate determined by the internal resistance and capacitance of said semiconductor substrate such that a time from when surplus carriers are injected into said substrate form said semiconductor integrated circuit until said surplus carriers are absorbed by one of said substrate bias voltage voltage generating circuits is substantially minimized, thereby reducing fluctuation of the desired potential.

Claim 23

The semiconductor integrated circuit device according to claim 17, wherein said substrate bias voltage generating circuits are positioned such that a distance from a first bias voltage generating circuit to a portion of said semiconductor integrated circuit furthest from said first bias voltage generating circuit is substantially equal to a distance from a second bias voltage generating circuit to a portion of said semiconductor integrated circuit furthest from said second bias voltage generating circuit.

Claim 24

The semiconductor integrated circuit device according to claim 18, wherein said bias voltage generating circuits each comprise a ring oscillator having an output, first and second diodes having respective anodes and cathodes, and a capacitor having first and second terminals, the first terminal of said capacitor being connected to the output of said ring oscillator, the cathode of said first diode being connected to the second terminal of said capacitor, the anode of said second diode being connected to the second terminal of said capacitor, the anode of said first diode being connected to said semiconductor substrate, and the cathode of said second diode being connected to a ground of said semiconductor integrated circuit.

Claim 25

The semiconductor integrated circuit device according to claim 18, wherein said semiconductor integrated circuit device includes CMOS memory cells.

Claim 26

The semiconductor integrated circuit device according to claim 18, wherein said semiconductor integrated circuit device includes CMOS inverters.