US5880992A — Electrically erasable and programmable read only …

Claim 1

Independent Claim 122 words

An electrically erasable and programmable read only memory device using a program voltage and a write enable signal for programming the electrically erasable programmable read only memory device, said device comprising: a memory array coupled to an address bus and a data bus; a register located in a predetermined memory area of the electrically erasable programmable read only memory device for latching a data bit from the data bus when the address of the register is selected, wherein the data bit functions as program enable or disable signal; and means for setting program enable or disable state of the electrically erasable programmable read only memory device in response to input of the output signal of the register and said write enable signal.

Claim 2

Dependent Claim 122 words

An electrically erasable and programmable read only memory device using a program voltage and a write enable signal for programming the electrically erasable programmable read only memory device, said device comprising: a memory array coupled to an address bus and a data bus; a register located in a predetermined memory area of the electrically erasable programmable read only memory device for latching a data bit from the data bus when the address of the register is selected, wherein the data bit functions as program enable or disable signal; and means for setting program enable or disable state of the electrically erasable programmable read only memory device in response to input of the output signal of the register and said write enable signal.

Claim 3

Dependent Claim 32 words

The electrically erasable programmable read only memory device as set forth in claim 1, wherein the register includes a D-flip flop which has a clock input connected with the write enable signal.

Claim 4

Dependent Claim 27 words

The electrically erasable programmable read only memory device as set forth in claim 1, wherein the program enable or disable state setting means includes an OR gate.

Claim 5

Dependent Claim 41 words

The electrically erasable programmable read only memory device as set forth in claim 1, wherein the program voltage supplied with the memory array is set to the same as the operating voltage of the electrically erasable programmable read only memory device.

Claim 6

Dependent Claim 148 words

An electronic circuit for enabling an electrically erasable programmable read only memory, comprising: a controller that outputs an inverted write enable signal; a data bus containing a plurality of data bit signals including a least significant bit; a D flip flop having an input terminal, an output terminal, and a clock terminal; and an OR gate having a first and a second input signal and an output signal, wherein one of said plurality of data bit signals is connected to said input of said D flip flop, said write enable signal is connected to said clock terminal of said D flip flop and a first of said inputs of said OR gate, said output of said D flip flop is connected to said second of said inputs of said OR gate, and said output of said OR gate enables or disables said electrically erasable programmable read only memory.

Claim 7

Dependent Claim 148 words

An electronic circuit for enabling an electrically erasable programmable read only memory, comprising: a controller that outputs an inverted write enable signal; a data bus containing a plurality of data bit signals including a least significant bit; a D flip flop having an input terminal, an output terminal, and a clock terminal; and an OR gate having a first and a second input signal and an output signal, wherein one of said plurality of data bit signals is connected to said input of said D flip flop, said write enable signal is connected to said clock terminal of said D flip flop and a first of said inputs of said OR gate, said output of said D flip flop is connected to said second of said inputs of said OR gate, and said output of said OR gate enables or disables said electrically erasable programmable read only memory.

Claim 8

Dependent Claim 20 words

The electronic circuit of claim 5, said least significant bit being connected to said input of said D flip flop.

Claim 9

Dependent Claim 31 words

The electronic circuit of claim 6, said D flip flop, said OR gate, said electrically erasable programmable read only memory, and said controller are powered by a +5 volt power supply.

Claim 10

Dependent Claim 23 words

The electronic circuit of claim 7, said electronic circuit operates in the absence of a voltage supply other than a +5 volt supply.

Claim 11

Dependent Claim 177 words

An electronic circuit for accessing memory in an electrically erasable programmable read only memory, comprising: an address bus connected to said electrically erasable programmable read only memory; a data bus connected to said electrically erasable programmable read only memory, said data bus containing a plurality of data bits including a least significant data bit; an OR gate having a first input and a second input and an output, said output connected to an enabling pin on said electrically erasable programmable read only memory for allowing writing to said electrically erasable programmable read only memory; a D flip flop having an input terminal, an output terminal, and a clock terminal, said output of said D flip flop being connected to said first input of said OR gate, one of said plurality of data bits being connected to said input of said D flip flop; and a controller outputting a write signal that is active low, said write signal being connected to both said clock input of said D flip flop and said second input of said OR gate.

Claim 12

Dependent Claim 177 words

An electronic circuit for accessing memory in an electrically erasable programmable read only memory, comprising: an address bus connected to said electrically erasable programmable read only memory; a data bus connected to said electrically erasable programmable read only memory, said data bus containing a plurality of data bits including a least significant data bit; an OR gate having a first input and a second input and an output, said output connected to an enabling pin on said electrically erasable programmable read only memory for allowing writing to said electrically erasable programmable read only memory; a D flip flop having an input terminal, an output terminal, and a clock terminal, said output of said D flip flop being connected to said first input of said OR gate, one of said plurality of data bits being connected to said input of said D flip flop; and a controller outputting a write signal that is active low, said write signal being connected to both said clock input of said D flip flop and said second input of said OR gate.

Claim 13

Dependent Claim 24 words

The electronic circuit of claim 9, said least significant bit of said data bus being connected to said input of said D flip flop.

Claim 14

Dependent Claim 15 words

The electronic circuit of claim 10, said circuit being powered by a single voltage source.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2002-03-08	2002-09-07	2003-03-09	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2006-03-08	2006-09-07	2007-03-09	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2010-03-08	2010-09-07	2011-03-09	$7700.00	Window Closed / Lapsed

Electrically erasable and programmable read only memory

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