Method for fabricating chip size packages using lamination process

Claim 1

A method for fabricating chip size packages, comprising the steps of: cutting a wafer, on which desired circuit patterns have been formed, into a plurality of wafer strips each having several dies, using a diamond saw; arranging the wafer strips on a stress reducing thermoplastic adhesive-coated polymer film supported by an annular frame in such a manner that they are aligned with each other while being uniformly spaced from one another by about 5 mm and in such a manner that the upper surface of each wafer strip faces the surface of the polymer film opposite to the annular frame; bonding the aligned wafer strips to the polymer film in accordance with a lamination process; forming a polymer dam made of an epoxy-based polymer on the surface of the polymer film, to which the wafer strips are bonded, around a wafer region where the wafer strips are disposed, filling an epoxy-based polymer in the wafer region defined by the polymer dam, thereby forming an encapsulant encapsulating the wafer strips, and curing the encapsulant; forming a double laminated polymer film to encapsulate the chips as an alternative encapsulation method; forming via holes at positions respectively corresponding to pads of chips through the polymer film, forming a solderable Ti/Ni/Cu metal thin film over the polymer film, forming a photoresist film over the solderable metal thin film, patterning the photoresist film, and patterning the metal thin film while using the patterned photoresist film as a mask, thereby forming an array of I/O pads for the chips; coating a flux on the I/O pads, arranging solder balls on the I/O pads, respectively, fusing the solder balls to the associated I/O pads using a solder reflow oven, and removing the flux using an organic solvent; and polishing the backside of the resulting epoxy encapsulated structure, and cutting several ten dies integrally formed in one lot into separate packages.

Claim 2

A method for fabricating chip size packages, comprising the steps of: cutting a wafer, on which desired circuit patterns have been formed, into a plurality of wafer strips each having several dies, using a diamond saw; arranging the wafer strips on a stress reducing thermoplastic adhesive-coated polymer film supported by an annular frame in such a manner that they are aligned with each other while being uniformly spaced from one another by about 5 mm and in such a manner that the upper surface of each wafer strip faces the surface of the polymer film opposite to the annular frame; bonding the aligned wafer strips to the polymer film in accordance with a lamination process; forming a polymer dam made of an epoxy-based polymer on the surface of the polymer film, to which the wafer strips are bonded, around a wafer region where the wafer strips are disposed, filling an epoxy-based polymer in the wafer region defined by the polymer dam, thereby forming an encapsulant encapsulating the wafer strips, and curing the encapsulant; forming a double laminated polymer film to encapsulate the chips as an alternative encapsulation method; forming via holes at positions respectively corresponding to pads of chips through the polymer film, forming a solderable Ti/Ni/Cu metal thin film over the polymer film, forming a photoresist film over the solderable metal thin film, patterning the photoresist film, and patterning the metal thin film while using the patterned photoresist film as a mask, thereby forming an array of I/O pads for the chips; coating a flux on the I/O pads, arranging solder balls on the I/O pads, respectively, fusing the solder balls to the associated I/O pads using a solder reflow oven, and removing the flux using an organic solvent; and polishing the backside of the resulting epoxy encapsulated structure, and cutting several ten dies integrally formed in one lot into separate packages.