US5878208A
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Method and system for instruction trace reconstruction utilizing limited output pins and bus monitoring
Assignee: International Business Machines Corp
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Filing: 1996-11-25
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Granted: 1999-03-02
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Expires: 2016-11-25
Abstract
Abstract Performance projections for processor systems and memory subsystems are important for a correct understanding of work loads within the system. An instruction trace is generally utilized to determine distribution of instructions, identification of register dependencies, branch path analyses and timing. One well known technique for reconstructing an instruction trace can be accomplished by monitoring bus traffic to determine address traces, data addresses and data during the trace, if the initial architectural state is known. The difficulty in reconstructing an instruction trace from monitored bus traffic can be decreased substantially if more definitive information regarding the actual instruction sequence can be obtained. An internal performance monitor within the processor system is utilized to detect each occurrence of the execution of a specified number of instructions and each occurrence of the execution of a specified number of some specific type of instruction such as load instructions or store instructions and generate an output in response to each such occurrence. This information, in addition to each detected occurrence of an external interrupt, is then utilized in combination with the monitored bus traffic to reconstruct an instruction trace utilizing a limited number of output pins.
Inventors
- 👤 Frank Eliot Levine
- 👤 William John Starke
- 👤 Edward Hugh Welbon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:29
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/30; G06F11/34; G06F11/3466; G06F11/349
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
156 words
A method of tracing the execution of a plurality of instructions within a processor system which includes a processor, a main memory, a cache memory and a bus interconnecting elements within said processor system, said method comprising the steps of: executing a series of instructions; initiating an instruction trace; in response to said initiation of said instruction trace, determining an initial state of said cache memory and monitoring subsequent instruction addresses, data addresses and data on said bus; monitoring an occurrence of each external interrupt which occurs within said processor system; detecting each occurrence of the execution of a predetermined number of instructions and each occurrence of the execution of a predetermined number of a specific type of instruction a single bit providing an output in response to each such detection; and thereafter, executing an instruction trace utilizing said monitored instruction addresses, data addresses and data, said initial state of said cache memory and said outputs.
Claim 2
Independent Claim
156 words
A method of tracing the execution of a plurality of instructions within a processor system which includes a processor, a main memory, a cache memory and a bus interconnecting elements within said processor system, said method comprising the steps of: executing a series of instructions; initiating an instruction trace; in response to said initiation of said instruction trace, determining an initial state of said cache memory and monitoring subsequent instruction addresses, data addresses and data on said bus; monitoring an occurrence of each external interrupt which occurs within said processor system; detecting each occurrence of the execution of a predetermined number of instructions and each occurrence of the execution of a predetermined number of a specific type of instruction a single bit providing an output in response to each such detection; and thereafter, executing an instruction trace utilizing said monitored instruction addresses, data addresses and data, said initial state of said cache memory and said outputs.
Claim 3
Dependent Claim
56 words
The method of tracing the execution of a plurality of instructions within a processor system according to claim 1, wherein said step of detecting each occurrence of the execution of a predetermined number of a specific type of instruction comprises the step of detecting each occurrence of the execution of a predetermined number of load instructions.
Claim 4
Dependent Claim
51 words
The method of tracing the execution of a plurality of load instructions within a processor system according to claim 2, wherein said step of detecting each occurrence of the execution of a predetermined number of load instructions comprises the step of detecting each occurrence of the execution of sixteen load instructions.
Claim 5
Dependent Claim
56 words
The method of tracing the execution of a plurality of instructions within a processor system according to claim 1, wherein said step of detecting each occurrence of the execution of a predetermined number of a specific type of instruction comprises the step of detecting each occurrence of the execution of a predetermined number of store instructions.
Claim 6
Dependent Claim
51 words
The method of tracing the execution of a plurality of store instructions within a processor system according to claim 4, wherein said step of detecting each occurrence of the execution of a predetermined number of store instructions comprises the step of detecting each occurrence of the execution of sixteen store instructions.
Claim 7
Dependent Claim
48 words
The method of tracing the execution of a plurality of instructions within a processor system according to claim 1, wherein said step of determining an initial state of said cache memory comprises the step of invalidating said cache memory in response to said initiation of said instruction trace.
Claim 8
Dependent Claim
64 words
The method of tracing the execution of a plurality of instructions within a processor system according to claim 1, wherein said processor system further includes a plurality of registers and buffers and wherein said method further includes the step of: copying the content of at least selected ones of said plurality of buffers and registers in response to said initiation of said instruction trace.
Claim 9
Dependent Claim
48 words
The method of tracing the execution of a plurality of instructions within a processor system according to claim 1, wherein said step of detecting each occurrence of the execution of a predetermined number of instructions comprises the step of detecting each occurrence of the execution of sixteen instructions.
Claim 10
Independent Claim
140 words
A system for tracing the execution of a plurality of instructions within a processor system which includes a processor, a main memory, a cache memory and a bus interconnecting elements within said processor system, said system comprising: means for executing a series of instructions; means for initiating an instruction trace; determining an initial state of said cache memory and monitoring subsequent instruction addresses, data addresses and data on said bus in response to said initiation of said instruction trace; means for monitoring an occurrence of each external interrupt which occurs within said processor system; and a performance monitor for detecting each occurrence of the execution of a predetermined number of instructions and each occurrence of the execution of a predetermined number of a specific type of instruction, and for providing a single bit output in response to each such detection.
Claim 11
Independent Claim
140 words
A system for tracing the execution of a plurality of instructions within a processor system which includes a processor, a main memory, a cache memory and a bus interconnecting elements within said processor system, said system comprising: means for executing a series of instructions; means for initiating an instruction trace; determining an initial state of said cache memory and monitoring subsequent instruction addresses, data addresses and data on said bus in response to said initiation of said instruction trace; means for monitoring an occurrence of each external interrupt which occurs within said processor system; and a performance monitor for detecting each occurrence of the execution of a predetermined number of instructions and each occurrence of the execution of a predetermined number of a specific type of instruction, and for providing a single bit output in response to each such detection.
Claim 12
Dependent Claim
47 words
The system for tracing the execution of a plurality of instructions within a processor system according to claim 9, wherein said means for determining an initial state of said cache memory comprises means for invalidating said cache memory in response to said initiation of said instruction trace.
Claim 13
Dependent Claim
63 words
The system for tracing the execution of a plurality of instructions within a processor system according to claim 9, wherein said processor system further includes a plurality of registers and buffers and wherein said system further includes: means for copying the content of at least selected ones of said plurality of buffers and registers in response to said initiation of said instruction trace.
Claim 14
Dependent Claim
32 words
The system for tracing the execution of a plurality of instructions within a processor system according to claim 9, wherein said performance monitor detects each occurrence of the execution of sixteen instructions.
Claim 15
Dependent Claim
34 words
The system for tracing the execution of a plurality of load instructions within a processor system according to claim 9, wherein said performance monitor detects each occurrence of the execution of sixteen load instructions.
Claim 16
Dependent Claim
34 words
The system for tracing the execution of a plurality of store instructions within a processor system according to claim 9, wherein said performance monitor detects each occurrence of the execution of sixteen store instructions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-01 | 2002-08-31 | 2003-03-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-01 | 2006-08-31 | 2007-03-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-01 | 2010-08-31 | 2011-03-02 | $7700.00 | Window Closed / Lapsed |