Method and apparatus for counting instruction types using bit masks and a programmable bit map

Claim 2

In a computer system having a processor in which instructions are fetched for potential execution, a counter for counting instructions in which each instruction is characterized by at least one instruction attribute of a plurality of instruction attributes, said counter comprising: at least one bit map storage means for storing a bit map comprising at least one map bit position, each map bit position representing an instruction attribute; setting means for setting at least one map bit at at least one predetermined map bit position before instruction decoding; bit mask storage means for storing a bit mask corresponding to one of said fetched instructions, said bit mask comprising at least one mask bit position, each mask bit position representing an instruction attribute, a mask bit at a corresponding mask bit position being set if said mask bit position represents an instruction attribute of said fetched instruction; and incrementing means for incrementing a count value associated with said at least one bit map based upon a comparison of said at least one bit map with said bit mask.

Claim 3

The counter of claim 1, wherein: each instruction attribute belongs to a corresponding attribute set, each bit map comprises at least one map field, each map field associated with one of said attribute sets and each map field comprising at least one map bit position, said bit mask comprises at least one mask field, each mask field is associated with one of said map fields and each mask field comprises at least one mask bit position, each mask bit position corresponding to one of said map bit positions such that each mask bit position and its corresponding map bit position correspond to the same instruction attribute; and said incrementing means comprises means for incrementing said count value associated with said at least one bit map if, for all map fields within said bit map, at at least one of said predetermined map bit positions within each map field, the mask bit at the mask bit position corresponding to said at least one of said predetermined map bit positions is set.

Claim 4

The counter of claim 1, wherein a plurality of main memory addresses are dedicated to said at least one bit map storage means, said map bit positions being set using main memory write operations.

Claim 5

The counter of claim 1, wherein a plurality of input/output port addresses are dedicated to said at least one bit map storage means, said map bit positions being set using input/output write operations.

Claim 6

The counter of claim 1, wherein said at least one bit map storage means is disposed in programmable memory.

Claim 7

The counter of claim 2, wherein a first of said attribute sets is a set of opcodes available for execution by said fetched instruction, each said instruction attribute of said first attribute set being a particular opcode.

Claim 8

The counter of claim 6, wherein each instruction attribute of a second attribute set is a particular addressing mode available to said fetched instruction.

Claim 9

The counter of claim 7, said second attribute set further comprising an instruction attribute denoting that no addressing mode is to be used by said fetched instruction.

Claim 10

The counter of claim 6, wherein each instruction attribute of a second of said attribute sets denotes a CPU register accessible by said fetched instruction.

Claim 11

The counter of claim 9, said second attribute set further comprising an instruction attribute denoting that no CPU register is to be accessed by said fetched instruction.

Claim 12

The counter of claim 6, wherein a second of said attribute sets comprises a first instruction attribute denoting that said fetched instruction has been executed and a second instruction attribute denoting that said fetched instruction has not been executed.

Claim 13

The counter of claim 1, wherein said incrementing means comprises: means for ANDing said bit mask with said at least one bit map to produce a logical result, said logical result associated with said at least one bit map; means for determining whether said bit mask and the logical result associated with said at least one bit map are identical; and means for incrementing said count value associated with said at least one bit map if the means for determining determines that the bit mask and the logical result associated with said at least one bit map are identical.

Claim 14

In a computer system having a processor in which instructions are fetched for potential execution, a counter for counting instructions in which each instruction is characterized by at least one instruction attribute of a plurality of instruction attributes, said counter comprising: at least one bit map register for storing a bit map comprising at least one map bit position, each map bit position representing an instruction attribute; setting logic for setting at least one map bit at at least one predetermined map bit position before instruction decoding; a bit mask register for storing a bit mask corresponding to one of said fetched instructions, said bit mask comprising at least one mask bit position, each mask bit position representing an instruction attribute, a mask bit at a corresponding mask bit position being set if said mask bit position represents an instruction attribute of said fetched instruction; and incrementing logic for incrementing a count value associated with said at least one bit map based upon a comparison of said at least one bit map with said bit mask.

Claim 15

In a computer system having a processor in which instructions are fetched for potential execution, a counter for counting instructions in which each instruction is characterized by at least one instruction attribute of a plurality of instruction attributes, said counter comprising: at least one bit map register for storing a bit map comprising at least one map bit position, each map bit position representing an instruction attribute; setting logic for setting at least one map bit at at least one predetermined map bit position before instruction decoding; a bit mask register for storing a bit mask corresponding to one of said fetched instructions, said bit mask comprising at least one mask bit position, each mask bit position representing an instruction attribute, a mask bit at a corresponding mask bit position being set if said mask bit position represents an instruction attribute of said fetched instruction; and incrementing logic for incrementing a count value associated with said at least one bit map based upon a comparison of said at least one bit map with said bit mask.

Claim 16

The counter of claim 13, wherein each instruction attribute belongs to a corresponding attribute set, each bit map comprises at least one map field, each map field associated with one of said attribute sets and each map field comprising at least one map bit position, said bit mask comprises at least one mask field, each mask field is associated with one of said map fields and each mask field comprises at least one mask bit position, each mask bit position corresponding to one of said map bit positions such that each mask bit position and its corresponding map bit position correspond to the same instruction attributes; and said incrementing logic comprises logic for incrementing said count value associated with said at least one bit map if, for all map fields within said bit map, at at least one of said predetermined map bit positions within each map field, the mask bit at the mask bit position corresponding to said at least one of said predetermined map bit positions is set.

Claim 17

The counter of claim 13, wherein a plurality of main memory addresses are dedicated to said at least one bit map register, said map bit positions being set using main memory write operations.

Claim 18

The counter of claim 13, wherein a plurality of input/output port addresses are dedicated to said at least one bit map register, said map bit positions being set using input/output write operations.

Claim 19

The counter of claim 13, wherein said at least one bit map register is disposed in programmable memory.

Claim 20

The counter of claim 14, wherein a first of said attribute sets is a set of opcodes available for execution by said fetched instruction, each said instruction attribute of said first attribute set being a particular opcode.

Claim 21

The counter of claim 18, wherein each instruction attribute of a second attribute set is a particular addressing mode available to said fetched instruction.

Claim 22

The counter of claim 19, said second attribute set further comprising an instruction attribute denoting that no addressing mode is to be used by said fetched instruction.

Claim 23

The counter of claim 18, wherein each instruction attribute of a second of said attribute sets denotes a CPU register accessible by said fetched instruction.

Claim 24

The counter of claim 21, said second attribute set further comprising an instruction attribute denoting that no CPU register is to be accessed by said fetched instruction.

Claim 25

The counter of claim 18, wherein a second of said attribute set comprises a first instruction attribute denoting that said fetched instruction has been executed and a second instruction attribute denoting that said fetched instruction has not been executed.

Claim 26

The counter of claim 13, wherein said incrementing logic comprises: a parallel ANDing logic circuit for ANDing said bit mask with said at least one bit map to produce a logical result, said logical result associated with said at least one bit map; a comparator for determining whether said bit mask and the logical result associated with said at least one bit map are identical; and a counting logic circuit for incrementing said count value associated with said at least one bit map if the means for determining determines that the bit mask and the logical result associated with said at least one bit map are identical.

Claim 27

A computer system comprising: main memory means for storing instructions; fetching means for fetching instructions from said main memory means for potential execution; system bus means for coupling said main memory means to said fetching means; counting means for counting said instructions, wherein each instruction is characterized by at least one instruction attribute of a plurality of instruction attributes, said counting means having: at least one bit map storage means for storing a bit map comprising at least one map bit position, each map bit position representing an instruction attribute; setting means for setting at least one map bit at at least one predetermined map bit position before instruction decoding; bit mask storage means for storing a bit mask corresponding to one of said fetched instructions, said bit mask comprising at least one mask bit position, each mask bit position representing an instruction attribute, a mask bit at a corresponding mask bit position being set if said mask bit position represents an instruction attribute of said fetched instruction; incrementing means for incrementing a count value associated with said at least one bit map based upon a comparison of said at lest one bit map with said bit mask.

Claim 28

A computer system comprising: main memory means for storing instructions; fetching means for fetching instructions from said main memory means for potential execution; system bus means for coupling said main memory means to said fetching means; counting means for counting said instructions, wherein each instruction is characterized by at least one instruction attribute of a plurality of instruction attributes, said counting means having: at least one bit map storage means for storing a bit map comprising at least one map bit position, each map bit position representing an instruction attribute; setting means for setting at least one map bit at at least one predetermined map bit position before instruction decoding; bit mask storage means for storing a bit mask corresponding to one of said fetched instructions, said bit mask comprising at least one mask bit position, each mask bit position representing an instruction attribute, a mask bit at a corresponding mask bit position being set if said mask bit position represents an instruction attribute of said fetched instruction; incrementing means for incrementing a count value associated with said at least one bit map based upon a comparison of said at lest one bit map with said bit mask.

Claim 29

A computer system comprising: a main memory for storing instructions; a fetching unit for fetching instructions from said main memory for potential execution; a system bus for coupling said main memory to said fetching unit; a counter for counting said instructions, wherein each instruction is characterized by at least one instruction attribute of a plurality of instruction attributes, said counter having: at least one bit map register for storing a bit map comprising at least one map bit position, each map bit position representing an instruction attribute; setting logic for setting at least one map bit at at least one predetermined map bit position before instruction decoding; a bit mask register for storing a bit mask corresponding to one of said fetched instructions, said bit mask comprising at least one mask bit position, each mask bit position representing an instruction attribute, a mask bit at a corresponding mask bit position being set if said mask bit position represents an instruction attribute of said fetched instruction; incrementing logic for incrementing a count value associated with said at least one bit map based upon a comparison of said at least one bit map with said bit mask.

Claim 30

A computer system comprising: a main memory for storing instructions; a fetching unit for fetching instructions from said main memory for potential execution; a system bus for coupling said main memory to said fetching unit; a counter for counting said instructions, wherein each instruction is characterized by at least one instruction attribute of a plurality of instruction attributes, said counter having: at least one bit map register for storing a bit map comprising at least one map bit position, each map bit position representing an instruction attribute; setting logic for setting at least one map bit at at least one predetermined map bit position before instruction decoding; a bit mask register for storing a bit mask corresponding to one of said fetched instructions, said bit mask comprising at least one mask bit position, each mask bit position representing an instruction attribute, a mask bit at a corresponding mask bit position being set if said mask bit position represents an instruction attribute of said fetched instruction; incrementing logic for incrementing a count value associated with said at least one bit map based upon a comparison of said at least one bit map with said bit mask.

Claim 31

In a computer system having a processor in which instructions are fetched for potential execution, a method for counting instructions in which each instruction is characterized by at least one instruction attribute of a plurality of instruction attributes, said method comprising the steps of: programming at least one bit map by setting at least one predetermined map bit of said at least one bit map, each map bit occupying a map bit position, each map bit position representing an instruction attribute; setting at least one mask bit of a bit mask, each mask bit occupying a mask bit position, each mask bit position representing an instruction attribute, said at least one mask bit being set if said mask bit position represents an instruction attribute of said fetched instruction; incrementing a count value associated with said at least one bit map based upon a comparison of said at least one bit map with said bit mask.

Claim 32

In a computer system having a processor in which instructions are fetched for potential execution, a method for counting instructions in which each instruction is characterized by at least one instruction attribute of a plurality of instruction attributes, said method comprising the steps of: programming at least one bit map by setting at least one predetermined map bit of said at least one bit map, each map bit occupying a map bit position, each map bit position representing an instruction attribute; setting at least one mask bit of a bit mask, each mask bit occupying a mask bit position, each mask bit position representing an instruction attribute, said at least one mask bit being set if said mask bit position represents an instruction attribute of said fetched instruction; incrementing a count value associated with said at least one bit map based upon a comparison of said at least one bit map with said bit mask.

Claim 33

The method of claim 27, wherein each instruction attribute belongs to a corresponding attribute set, each bit map comprises at least one map field, each map field associated with one of said attribute sets and each map field comprising at least one map bit position, said bit mask comprises at least one mask field, each mask field associated with one of said map fields and each mask field comprising at least one mask bit position, each mask bit position corresponding to one of said map bit positions such that each mask bit position and its corresponding map bit position correspond to the same instruction attribute; said incrementing step comprising the step of incrementing said count value associated with said at least one bit map if, for all map fields within said at least one bit map, at at least one of said predetermined map bit positions within each map field, the mask bit at the mask bit position corresponding to said at least one of said predetermined map bit positions is set.

Claim 34

The counter of claim 28, wherein a first of said attribute sets is a set of opcodes available for execution by said fetched instruction, each said instruction attribute of said first attribute set being a particular opcode.

Claim 35

The counter of claim 29, wherein each instruction attribute of a second attribute set is a particular addressing mode available to said fetched instruction.

Claim 36

The counter of claim 30, said second attribute set further comprising in instruction attribute denoting that no addressing mode is to be used by said fetched instruction.

Claim 37

The counter of claim 29, wherein each instruction attribute of a second of said attribute sets denotes a CPU register accessible by said fetched instruction.

Claim 38

The counter of claim 32, said second attribute set further comprising an instruction attribute denoting that no CPU register is to be accessed by said fetched instruction.

Claim 39

The counter of claim 29, wherein a second of said attribute sets comprises a first instruction attribute denoting that said fetched instruction has been executed and a second instruction attribute denoting that said fetched instruction has not been executed.

Claim 40

The method of claim 27, said incrementing step comprising the steps of: ANDing said bit mask with said at least one bit map to produce a logical result, said logical result associated with said at least one bit map; determining whether said bit mask and the logical result associated with said at least one bit map are identical; and incrementing the count value associated with said at least one bit map if the means for determining determines that the bit mask and the logical result associated with said at least one bit map are identical.