Method for counting simultaneously many conditions

Abstract

Abstract PURPOSE:To reduce a circuit scale by storing in advance a formation and an unformation of a composite conditional expression, on a memory by '1' and '0', and deciding simultaneously the formation and the unformation of each composite conditional expression, at every record of a counting object. CONSTITUTION:With respect to all combinations [when the number of unit conditional expressions is denoted as (a), the number of combinations is 2<a> pieces] of a formation and an unformation of each unit conditional expression, an entry of a memory 20 is prepared. Subsequently, each bit of its entry is allocated to designated composite conditional expressions, respectively, and a 'composite condition formation' (namely, 'counting instruction') is set in advance to the bit concerned of the entry corresponding to the combination of the unit conditional expression by which each composite conditional expression is formed in the preparation stage. After the counting processing has been started, a result of decision of the unit conditional expression is set to a result latch in the same way as a conventional system at every record, and thereafter, the memory 20 is read out by the contents of the result latch. If the bit to which the 'composite condition formation' has been set exists in the entry which has been read out, counting is executed by a counting circuit 4 corresponding thereto. In this way, a circuit scale is reduced, and also, a limit of the number of allowable capacities of OR in the composite conditional expression can be eliminated.

Inventors

• 👤 Haruo Hayamizu
• 👤 速水　治夫

Bibliographic Details