Semiconductor integrated circuit

Claim 2

A semiconductor integrated circuit comprising N-channel and P-channel thin film transistors formed on insulating surface, each of said N-channel and P-channel thin film transistors having a gate electrode comprising a material of which work function is smaller than 5 eV, wherein a channel length of the P-channel thin film transistor is made shorter than that of the N-channel film transistor by at least 20% for approximating an absolute value of a threshold voltage of the P-channel thin film transistor to that of the N-channel thin film transistor while the threshold voltage of the N-channel TFT is kept large enough to prevent it from being rendered in a normally-on state; and wherein a width of the gate electrode of the P-channel thin film transistor in a direction along a source region and a drain region is shorter than that of the N-channel thin film transistor by at least 25%.

Claim 3

A semiconductor integrated circuit according to claim 1 wherein the gate electrode of said N-channel thin film transistor comprises the same material as the gate electrode of said P-channel thin film transistor.

Claim 4

A semiconductor integrated circuit according to claim 1 wherein the gate electrode of said N-channel thin film transistor is electrically connected to the gate electrode of said P-channel thin film transistor.

Claim 5

A semiconductor integrated circuit according to claim 1 wherein a channel region of said N-channel and P-channel thin film transistors has an impurity of which concentration is lower than 1×10 18 atoms/cm 3 and said impurity controls conductivity type.

Claim 6

A semiconductor integrated circuit according to claim 4 wherein said impurity of said N-channel and P-channel thin film transistors are phosphorus and boron respectively.

Claim 7

A semiconductor integrated circuit according to claim 4 further comprising an element selected from a group consisting of carbon, nitrogen and oxygen in the channel region of said N-channel and P-channel thin film transistors, wherein each concentration of the carbon, nitrogen and oxygen is lower than 1×10 19 atoms/cm 3 .

Claim 8

A semiconductor integrated circuit according to claim 1 wherein said N-channel and P-channel thin film transistors constitute a pair of complementary transistors.

Claim 9

A semiconductor integrated circuit according to claim 1 wherein said gate electrode comprises aluminum.

Claim 10

A semiconductor integrated circuit comprising: an N-channel thin film transistor formed on an insulating surface; and a P-channel thin film transistor formed on said insulating surface, said P-channel thin film transistor having a substantially same cross sectional structure as said N-channel thin film transistor; wherein a channel length of the P-channel thin film transistor is made shorter than that of the N-channel thin film transistor by at least 20% for approximating an absolute value of a threshold voltage of the P-channel thin film transistor to that of the N-channel thin film transistor, and wherein a width of a gate electrode of the P-channel thin film transistor in a direction along a source region and a drain region is shorter than that of the N-channel thin film transistor by at least 25%.

Claim 11

A semiconductor integrated circuit comprising: an N-channel thin film transistor formed on an insulating surface; and a P-channel thin film transistor formed on said insulating surface, said P-channel thin film transistor having a substantially same cross sectional structure as said N-channel thin film transistor; wherein a channel length of the P-channel thin film transistor is made shorter than that of the N-channel thin film transistor by at least 20% for approximating an absolute value of a threshold voltage of the P-channel thin film transistor to that of the N-channel thin film transistor, and wherein a width of a gate electrode of the P-channel thin film transistor in a direction along a source region and a drain region is shorter than that of the N-channel thin film transistor by at least 25%.

Claim 12

A semiconductor integrated circuit according to claim 9 wherein said N-channel and P-channel thin film transistors constitute a pair of complementary transistors.

Claim 13

A semiconductor integrated circuit according to claim 9 wherein said N-channel and P-channel thin film transistors constitute a pair of complementary transistors formed by a common process.

Claim 14

A semiconductor integrated circuit according to claim 9 wherein at least one of said N-channel and P-channel thin film transistors has an offset region.

Claim 15

A semiconductor integrated circuit according to claim 9 wherein said N-channel and P-channel thin film transistors have at lease one of an offset structure and an LDD structure.

Claim 16

A semiconductor integrated circuit comprising N-channel and P-channel thin film transistors formed on insulating surface, each of said N-channel and P-channel thin film transistors having a gate electrode comprising a material of which work function is smaller than 5 eV, wherein a channel length of the P-channel thin film transistor is made shorter than that of the N-channel thin film transistor by at least 20% for approximating an absolute value of a threshold voltage of the P-channel thin film transistor to that of the N-channel thin film transistor wherein a channel region of said N-channel and P-channel thin film transistor has a (111) plane, and wherein a width of the gate electrode of the P-channel thin film transistor in a direction along a source region and a drain region is shorter than that of the N-channel thin film transistor by at least 25%.

Claim 17

A semiconductor integrated circuit comprising N-channel and P-channel thin film transistors formed on insulating surface, each of said N-channel and P-channel thin film transistors having a gate electrode comprising a material of which work function is smaller than 5 eV, wherein a channel length of the P-channel thin film transistor is made shorter than that of the N-channel thin film transistor by at least 20% for approximating an absolute value of a threshold voltage of the P-channel thin film transistor to that of the N-channel thin film transistor wherein a channel region of said N-channel and P-channel thin film transistor has a (111) plane, and wherein a width of the gate electrode of the P-channel thin film transistor in a direction along a source region and a drain region is shorter than that of the N-channel thin film transistor by at least 25%.

Claim 18

A semiconductor integrated circuit according to claim 14 wherein said N-channel and P-channel thin film transistors constitute a pair of complementary transistors.

Claim 19

A semiconductor integrated circuit according to claim 14 wherein said gate electrode comprises aluminum.

Claim 20

A semiconductor integrated circuit comprising: an N-channel thin film transistor and a P-channel thin film transistor electrically connected to said N-channel thin film transistor over a substrate, each of said thin film transistors comprising: a semiconductor layer having source and drain regions, and a channel region interposed between said source and drain region; and a gate electrode comprising a material of which work function is less than 5 eV and formed adjacent to said channel region with a gate insulating film interposed therebetween, wherein said source and drain regions are formed in a self-alignment manner with respect to said gate electrode; wherein the width of the gate electrode of said P-channel thin film transistor in a direction along the source and drain regions is shorter than that of said N-channel transistor by at least 25%.

Claim 21

A semiconductor integrated circuit comprising: an N-channel thin film transistor and a P-channel thin film transistor electrically connected to said N-channel thin film transistor over a substrate, each of said thin film transistors comprising: a semiconductor layer having source and drain regions, and a channel region interposed between said source and drain region; and a gate electrode comprising a material of which work function is less than 5 eV and formed adjacent to said channel region with a gate insulating film interposed therebetween, wherein said source and drain regions are formed in a self-alignment manner with respect to said gate electrode; wherein the width of the gate electrode of said P-channel thin film transistor in a direction along the source and drain regions is shorter than that of said N-channel transistor by at least 25%.

Claim 22

A semiconductor integrated circuit according to claim 17 wherein the channel region of said N-channel and P-channel thin film transistors has a (111) plane.

Claim 23

A semiconductor integrated circuit according to claim 17 wherein a channel length of said P-channel transistor is shorter than that of said N-channel transistor by at least 20%.

Claim 24

A semiconductor integrated circuit according to claim 17 wherein said gate electrode comprises aluminum.

Claim 25

A semiconductor integrated circuit according to claim 17 wherein said gate electrode of the N-channel and P-channel transistor is provided with an anodic oxide film on at least side surfaces of said gate electrode, said anodic oxide film comprising an oxide of the material of said gate electrode.

Claim 26

A semiconductor integrated circuit according to claim 21 wherein said source and drain regions are offset from side edges of said gate electrode by a distance approximately equal to a thickness of said anodic oxide film.

Claim 27

A semiconductor integrated circuit comprising: an N-channel thin film transistor and a P-channel thin film transistor electrically connected to said N-channel thin film transistor over a substrate, the P-channel thin film transistor having a substantially same cross sectional structure as the N-channel thin film transistor, each of the thin film transistors comprising: a semiconductor layer having a source region and a drain region, and a channel region interposed between said source region and said drain region; and a gate electrode formed adjacent to said channel region with a gate insulating film interposed therebetween, wherein a channel length of the P-channel thin film transistor is shorter than that of the N-channel thin film transistor by at least 20% for approximating an absolute value of a threshold voltage of the P-channel thin film transistor to that of the N-channel thin film transistor, and wherein a width of the gate electrode of the P-channel thin film transistor in a direction along the source region and the drain region is 25 to 80% of that of the N-channel thin film transistor.

Claim 28

A semiconductor integrated circuit comprising: an N-channel thin film transistor and a P-channel thin film transistor electrically connected to said N-channel thin film transistor over a substrate, the P-channel thin film transistor having a substantially same cross sectional structure as the N-channel thin film transistor, each of the thin film transistors comprising: a semiconductor layer having a source region and a drain region, and a channel region interposed between said source region and said drain region; and a gate electrode formed adjacent to said channel region with a gate insulating film interposed therebetween, wherein a channel length of the P-channel thin film transistor is shorter than that of the N-channel thin film transistor by at least 20% for approximating an absolute value of a threshold voltage of the P-channel thin film transistor to that of the N-channel thin film transistor, and wherein a width of the gate electrode of the P-channel thin film transistor in a direction along the source region and the drain region is 25 to 80% of that of the N-channel thin film transistor.

Claim 29

A semiconductor integrated circuit according to claim 23 wherein impurity concentration in the channel region of the N-channel and P-channel thin film transistors is lower than 1×10 18 atoms/cm 3 and the impurity controls conductivity type of the semiconductor layer.

Claim 30

A semiconductor integrated circuit according to claim 24 wherein said impurity in the channel region of the N-channer and P-channel thin film transistors are phosphorus and boron respectively.

Claim 31

A semiconductor integrated circuit according to claim 24 further comprising an element selected from a group consisting of carbon, nitrogen and oxygen in the channel region of the N-channel and P-channel thin film transistors, wherein each concentration of the carbon, nitrogen and oxygen is lower than 1×10 19 atoms/cm 3 .

Claim 32

A semiconductor integrated circuit according to claim 23 wherein said gate electrode comprises aluminum.

Claim 33

A semiconductor integrated circuit according to claim 23 wherein said channel region of the N-channel and P-channel thin film transistors has a (111) plane.

Claim 34

A semiconductor integrated circuit according to claim 23 wherein a difference of the absolute value of the threshold voltage between the P-channel thin film transistor and the N-channel thin film transistor is 0.4 V or less.

Claim 35

A semiconductor integrated circuit comprising: an N-channel thin film transistor and a P-channel thin film transistor electrically connected to said N-channel thin film transistor over a substrate, the P-channel thin film transistor having a substantially same cross-sectional structure as the N-channel thin film transistor, each of the thin film transistors comprising: a semiconductor layer having a source region and a drain region, and a channel region interposed between said source region and said drain region; and a gate electrode formed adjacent to said channel region with a gate insulating film interposed therebetween, wherein a channel length of the P-channel thin film transistor is shorter than that of the N-channel thin film transistor by at least 20% for approximating an absolute value of a threshold voltage of the P-channel thin film transistor to that of the N-channel thin film transistor, and wherein a width of the gate electrode of the P-channel thin film transistor in a direction along the source region and the drain region is shorter than that of the N-channel thin film transistor by at least 25%.

Claim 36

A semiconductor integrated circuit comprising: an N-channel thin film transistor and a P-channel thin film transistor electrically connected to said N-channel thin film transistor over a substrate, the P-channel thin film transistor having a substantially same cross-sectional structure as the N-channel thin film transistor, each of the thin film transistors comprising: a semiconductor layer having a source region and a drain region, and a channel region interposed between said source region and said drain region; and a gate electrode formed adjacent to said channel region with a gate insulating film interposed therebetween, wherein a channel length of the P-channel thin film transistor is shorter than that of the N-channel thin film transistor by at least 20% for approximating an absolute value of a threshold voltage of the P-channel thin film transistor to that of the N-channel thin film transistor, and wherein a width of the gate electrode of the P-channel thin film transistor in a direction along the source region and the drain region is shorter than that of the N-channel thin film transistor by at least 25%.

Claim 37

A semiconductor integrated circuit comprising: an N-channel thin film transistor and P-channel thin film transistor electrically connected to said N-channel thin film transistor over a substrate, the P-channel thin film transistor having a substantially same cross sectional structure as the N-channel thin film transistor, each of the film transistors comprising: a semiconductor layer having a source region and a drain region, and a channel region interposed between said source region and said drain region; at least one of an offset region and a lightly doped drain region each of which is interposed between said drain region and said channel region; and a gate electrode formed adjacent to said channel region with a gate insulating film interposed therebetween, wherein a channel length of the P-channel thin film transistor is shorter than that of the N-channel thin film transistor by at least 20% for approximating an absolute value of a threshold voltage of the P-channel thin film transistor to that of the N-channel thin film transistor, and wherein a width of the gate electrode of the P-channel thin film transistor in a direction along the source region and the drain region is shorter than that of the N-channel thin film transistor by at least 25%.

Claim 38

A semiconductor integrated circuit comprising: an N-channel thin film transistor and P-channel thin film transistor electrically connected to said N-channel thin film transistor over a substrate, the P-channel thin film transistor having a substantially same cross sectional structure as the N-channel thin film transistor, each of the film transistors comprising: a semiconductor layer having a source region and a drain region, and a channel region interposed between said source region and said drain region; at least one of an offset region and a lightly doped drain region each of which is interposed between said drain region and said channel region; and a gate electrode formed adjacent to said channel region with a gate insulating film interposed therebetween, wherein a channel length of the P-channel thin film transistor is shorter than that of the N-channel thin film transistor by at least 20% for approximating an absolute value of a threshold voltage of the P-channel thin film transistor to that of the N-channel thin film transistor, and wherein a width of the gate electrode of the P-channel thin film transistor in a direction along the source region and the drain region is shorter than that of the N-channel thin film transistor by at least 25%.

Claim 39

A semiconductor integrated circuit according to claim 31 wherein impurity concentration in the channel region of the N-channel and P-channel thin film transistors is lower than 1×10 18 atoms/cm 3 and the impurity controls conductivity type of the semiconductor layer.

Claim 40

A semiconductor integrated circuit according to claim 32 wherein said impurity in the channel region of the N-channel and P-channel thin film transistors are phosphorus and boron respectively.

Claim 41

A semiconductor integrated circuit according to claim 32 further comprising an element selected from a group consisting of carbon, nitrogen and oxygen in the channel region of the N-channel and P-channel thin film transistors, wherein each concentration of the carbon, nitrogen and oxygen is lower than 1×10 19 atoms/cm 3 .

Claim 42

A semiconductor integrated circuit according to claim 31 wherein said gate electrode comprises aluminum.

Claim 43

A semiconductor integrated circuit according to claim 31 wherein said channel region of the N-channel and P-channel thin film transistors has a (111) plane.

Claim 44

A semiconductor integrated circuit according to claim 31 wherein said approximating means that a difference of the absolute value of the threshold voltage between the P-channel thin film transistor and the N-channel thin film transistor is 0.4 V or less.

Claim 45

A semiconductor integrated circuit comprising: an N-channel thin film transistor and P-channel thin film transistor electrically connected to said N-channel thin film transistor over a substrate, the P-channel thin film transistor having a substantially same cross sectional structure as the N-channel thin film transistor, each of the thin film transistors comprising: a semiconductor layer having a source region and a drain region, and a channel region interposed between said source region and said drain region; and a gate electrode formed adjacent to said channel region with a gate insulating film interposed therebetween, wherein a channel length of the P-channel thin film transistor is shorter than that of the N-channel thin film transistor by at least 20%, and wherein a width of the gate electrode of the P-channel thin film transistor in a direction along the source region and the drain region is 25 to 80% of that of the N-channel thin film transistor.

Claim 46

A semiconductor integrated circuit comprising: an N-channel thin film transistor and P-channel thin film transistor electrically connected to said N-channel thin film transistor over a substrate, the P-channel thin film transistor having a substantially same cross sectional structure as the N-channel thin film transistor, each of the thin film transistors comprising: a semiconductor layer having a source region and a drain region, and a channel region interposed between said source region and said drain region; and a gate electrode formed adjacent to said channel region with a gate insulating film interposed therebetween, wherein a channel length of the P-channel thin film transistor is shorter than that of the N-channel thin film transistor by at least 20%, and wherein a width of the gate electrode of the P-channel thin film transistor in a direction along the source region and the drain region is 25 to 80% of that of the N-channel thin film transistor.

Claim 47

A semiconductor integrated circuit according to claim 38 wherein impurity concentration in the channel region of the N-channel and P-channel thin film transistors is lower than 1×10 18 atoms/cm 3 and the impurity controls conductivity type of the semiconductor layer.

Claim 48

A semiconductor integrated circuit according to claim 39 wherein said impurity in the channel region of the N-channel and P-channel thin film transistors are phosphorus and boron respectively.

Claim 49

A semiconductor integrated circuit according to claim 39 further comprising an element selected from a group consisting of carbon, nitrogen and oxygen in the channel region of the N-channel and P-channel thin film transistors, wherein each concentration of the carbon, nitrogen and oxygen is lower than 1×10 19 atoms/cm 3 .

Claim 50

A semiconductor integrated circuit according to claim 38 wherein said gate electrode comprises aluminum.

Claim 51

A semiconductor integrated circuit according to claim 38 wherein said channel region of the N-channel and P-channel thin film transistors has a (111) plane.

Claim 52

A semiconductor integrated circuit according to claim 38 further comprising at least one of an offset region and lightly doped drain region, wherein each of the offset region and the lightly doped drain region is interposed between said drain region and said channel region.

Claim 53

A semiconductor integrated circuit comprising: an N-channel thin film transistor and a P-channel thin film transistor electrically connected to said N-channel thin film transistor over a substrate, the P-channel thin film transistor having a substantially same cross-sectional structure as the N-channel thin film transistor, each of the thin film transistors comprising: a semiconductor layer having a source region and a drain region, and a channel region interposed between said source region and said drain region; and a gate electrode formed adjacent to said channel region with a gate insulating film interposed therebetween, wherein a channel length of the P-channel thin film transistor is shorter than that of the N-channel thin film transistor by at least 20%, and wherein a width of the gate electrode of the P-channel thin film transistor in a direction along the source region and the drain region is shorter than that of the N-channel thin film transistor by at least 25%.

Claim 54

A semiconductor integrated circuit comprising: an N-channel thin film transistor and a P-channel thin film transistor electrically connected to said N-channel thin film transistor over a substrate, the P-channel thin film transistor having a substantially same cross-sectional structure as the N-channel thin film transistor, each of the thin film transistors comprising: a semiconductor layer having a source region and a drain region, and a channel region interposed between said source region and said drain region; and a gate electrode formed adjacent to said channel region with a gate insulating film interposed therebetween, wherein a channel length of the P-channel thin film transistor is shorter than that of the N-channel thin film transistor by at least 20%, and wherein a width of the gate electrode of the P-channel thin film transistor in a direction along the source region and the drain region is shorter than that of the N-channel thin film transistor by at least 25%.