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US5148244A Expired / Lapsed US ⏱️ 0.0 years remaining

Enhancement-fet and depletion-fet with different gate length formed in compound semiconductor substrate

Assignee: Toshiba Corp
•
Filing: 1991-02-11
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Granted: 1992-09-15
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Expires: 2011-02-11
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Abstract

Abstract This invention provides an E/D integrated circuit obtained by connecting an enhancement transistor serving as a switching transistor to a depletion transistor serving as a load and having a gate length larger than a gate length of the enhancement transistor in series with each other.

Inventors

  • 👤 Hiroshi Iwasaki

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 10:12
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/86; H10D84/82; H10D84/83

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 126 words
A semiconductor integrated circuit comprising: an enhancement transistor having a gate and a current path and serving as a switch, the gate of said enhancement transistor having a first gate length and a first gate width; and a depletion transistor having a gate and a current path and serving as a load, the gate of said depletion transistor having a second gate length and a second gate width; the current path of said enhancement transistor connected in series with the current path of said depletion transistor, the second gate length of said depletion transistor being greater than the first gate length of said enhancement transistor, and the second gate width of said depletion transistor being substantially equal to the first gate width of said enhancement transistor.
Claim 2
Dependent Claim 126 words
A semiconductor integrated circuit comprising: an enhancement transistor having a gate and a current path and serving as a switch, the gate of said enhancement transistor having a first gate length and a first gate width; and a depletion transistor having a gate and a current path and serving as a load, the gate of said depletion transistor having a second gate length and a second gate width; the current path of said enhancement transistor connected in series with the current path of said depletion transistor, the second gate length of said depletion transistor being greater than the first gate length of said enhancement transistor, and the second gate width of said depletion transistor being substantially equal to the first gate width of said enhancement transistor.
Claim 3
Dependent Claim 31 words
The semiconductor integrated circuit according to claim 1, wherein the second gate length of said depletion transistor is not less than 1.5 times the first gate length of said enhancement transistor.
Claim 4
Dependent Claim 18 words
The semiconductor integrated circuit according to claim 1, wherein said depletion transistor and said enhancement transistor are MESFETs.
Claim 5
Dependent Claim 18 words
The semiconductor integrated circuit according to claim 3, wherein said MESFETs are formed in a compound semiconductor substrate.
Claim 6
Dependent Claim 17 words
The semiconductor integrated circuit according to claim 4, wherein said compound semiconductor substrate is made of GaAs.
Claim 7
Dependent Claim 125 words
A semiconductor integrated circuit comprising: an enhancement transistor having a gate and a current path and serving as a switch, the gate of said enhancement transistor having a first gate length and a first gate width; and a depletion transistor having a gate and a current path and serving as a load, the gate of said depletion transistor having a second gate length and a second gate width; the current path of said enhancement transistor connected in series with the current path of said depletion transistor, the second gate length of said depletion transistor being greater than the first gate length of said enhancement transistor, and the second gate width of said depletion transistor being greater than the first gate width of said enhancement transistor.
Claim 8
Dependent Claim 125 words
A semiconductor integrated circuit comprising: an enhancement transistor having a gate and a current path and serving as a switch, the gate of said enhancement transistor having a first gate length and a first gate width; and a depletion transistor having a gate and a current path and serving as a load, the gate of said depletion transistor having a second gate length and a second gate width; the current path of said enhancement transistor connected in series with the current path of said depletion transistor, the second gate length of said depletion transistor being greater than the first gate length of said enhancement transistor, and the second gate width of said depletion transistor being greater than the first gate width of said enhancement transistor.
Claim 9
Dependent Claim 31 words
The semiconductor integrated circuit according to claim 6, wherein the second gate length of said depletion transistor is not less than 1.5 times the first gate length of said enhancement transistor.
Claim 10
Dependent Claim 55 words
The semiconductor integrated circuit according to claim 6, wherein when the second gate length and the second gate width of said depletion transistor are represented by Lg1 and Wg1, and the first gate length and the first gate width of said enhancement transistor are represented by Lg2 and Wg2, the following equation is satisfied: ##EQU6##
Claim 11
Dependent Claim 18 words
The semiconductor integrated circuit according to claim 6, wherein said depletion transistor and said enhancement transistor are MESFETs.
Claim 12
Dependent Claim 18 words
The semiconductor integrated circuit according to claim 11, wherein said MESFETs are formed in a compound semiconductor substrate.
Claim 13
Dependent Claim 17 words
The semiconductor integrated circuit according to claim 10, wherein said compound semiconductor substrate is made of GaAs.

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Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-09-15 1996-03-16 1996-09-15 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-09-15 2000-03-16 2000-09-15 $3760.00 Window Closed / Lapsed
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