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Patent US5875134A successfully refreshed from Google Patents.
US5875134A
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US
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Data communication for memory
Assignee: Round Rock Research LLC
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Filing: 1997-09-08
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Granted: 1999-02-23
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Expires: 2017-09-08
Abstract
Abstract A memory circuit is described which has an output data strobe signal that indicates when valid data is available on the output lines. Several alternate signals and circuits are described which can be used for the output strobe signal. An echo clock signal is described which selectively follows an input clock signal in a synchronous memory system and indicated when valid output data is available. The output strobe signal is used to speed the reading of data from the output line by allowing a microprocessor, or other external circuit, to read the data from the output lines as soon as it is valid, thereby eliminating the need to wait a specified period of time.
Inventors
- 👤 Eugene H. Cloud
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:35
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C7/00; G11C7/10; G11C7/1051; G11C7/1063; G11C11/4076; G11C7/22
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
96 words
An integrated circuit memory device comprising: a trigger circuit configured to receive a clock input signal and a control signal, the trigger circuit having an output for providing a pulsed signal which is generated in response to the clock input signal and the control signal, the pulsed signal being delayed from the clock input signal and associated with data output from the memory device; and an output driver circuit adapted to receive the pulsed signal and provide an output data strobe signal indicating when valid data is available from the memory device on data communication lines.
Claim 2
Dependent Claim
96 words
An integrated circuit memory device comprising: a trigger circuit configured to receive a clock input signal and a control signal, the trigger circuit having an output for providing a pulsed signal which is generated in response to the clock input signal and the control signal, the pulsed signal being delayed from the clock input signal and associated with data output from the memory device; and an output driver circuit adapted to receive the pulsed signal and provide an output data strobe signal indicating when valid data is available from the memory device on data communication lines.
Claim 3
Dependent Claim
27 words
The integrated circuit memory device of claim 1 wherein the pulsed signal is synchronized with the start of the output data from the integrated circuit memory device.
Claim 4
Dependent Claim
43 words
The integrated circuit memory device of claim 1 wherein the pulsed signal is out of phase with the start of the output data from the integrated circuit memory device, such that a transition of the pulsed signal occurs during the output of data.
Claim 5
Dependent Claim
25 words
The integrated circuit memory device of claim 1 wherein the pulsed signal has a frequency which is n-times a frequency of the clock input signal.
Claim 6
Dependent Claim
25 words
The integrated circuit memory device of claim 1 wherein the pulsed signal has a frequency which is two-times a frequency of the clock input signal.
Claim 7
Dependent Claim
33 words
The integrated circuit memory device of claim 1 wherein both rising and falling edges of the pulsed signal are synchronized with the start of the output data from the integrated circuit memory device.
Claim 8
Dependent Claim
18 words
The integrated circuit memory device of claim 1 wherein the pulsed signal is inhibited during non-read memory operations.
Claim 9
Dependent Claim
57 words
A synchronous memory device comprising: an input for receiving a clock signal; an output for providing an output strobe signal which substantially follows the clock signal during a data read operation, and transitions of the output strobe signal indicate when data is available on data output lines; and a generating circuit for producing the output strobe signal.
Claim 10
Dependent Claim
57 words
A synchronous memory device comprising: an input for receiving a clock signal; an output for providing an output strobe signal which substantially follows the clock signal during a data read operation, and transitions of the output strobe signal indicate when data is available on data output lines; and a generating circuit for producing the output strobe signal.
Claim 11
Dependent Claim
22 words
The synchronous memory device of claim 8 wherein the output strobe signal also substantially follows the clock signal during non-data read operations.
Claim 12
Dependent Claim
29 words
The synchronous memory device of claim 8 wherein either a rising or falling transition of the output strobe signal indicates that data is available on the data output lines.
Claim 13
Dependent Claim
23 words
The synchronous memory device of claim 8 wherein the output strobe signal indicates a start of data transmission on the data output lines.
Claim 14
Dependent Claim
114 words
A memory system comprising: a microprocessor; and a memory module coupled to the microprocessor for bi-directional data communication, the memory module comprising: a plurality of synchronous memories, a trigger circuit configured to receive a clock input signal on a clock signal input, the trigger circuit having an output for providing a pulsed signal which is generated in response to the clock input signal, the pulsed signal being delayed from the clock input signal and associated with data output from the memory module, and an output driver circuit adapted to receive the pulsed signal and provide an output data strobe signal indicating when valid data is available from the memory module on data communication lines.
Claim 15
Dependent Claim
114 words
A memory system comprising: a microprocessor; and a memory module coupled to the microprocessor for bi-directional data communication, the memory module comprising: a plurality of synchronous memories, a trigger circuit configured to receive a clock input signal on a clock signal input, the trigger circuit having an output for providing a pulsed signal which is generated in response to the clock input signal, the pulsed signal being delayed from the clock input signal and associated with data output from the memory module, and an output driver circuit adapted to receive the pulsed signal and provide an output data strobe signal indicating when valid data is available from the memory module on data communication lines.
Claim 16
Dependent Claim
26 words
The memory system of claim 12 wherein the output data strobe signal is synchronized with the start of the valid output data from the memory module.
Claim 17
Independent Claim
86 words
A method of reading data from a synchronous memory device, the method comprising the steps of: providing a clock signal to the synchronous memory device; initiating a memory read operation; generating an echo clock signal which substantially follows the clock signal during the memory read operation; outputting the echo clock signal from the synchronous memory device; monitoring the echo clock signal with an external processor or chip set; and reading data output from the synchronous memory device in response to transition of the echo clock signal.
Claim 18
Independent Claim
86 words
A method of reading data from a synchronous memory device, the method comprising the steps of: providing a clock signal to the synchronous memory device; initiating a memory read operation; generating an echo clock signal which substantially follows the clock signal during the memory read operation; outputting the echo clock signal from the synchronous memory device; monitoring the echo clock signal with an external processor or chip set; and reading data output from the synchronous memory device in response to transition of the echo clock signal.
Claim 19
Dependent Claim
42 words
The method of claim 14 further comprising the steps of synchronizing the output data strobe signal with data output from the synchronous memory device so that a transition of the output data strobe signal corresponds to a start of the data output.
Claim 20
Dependent Claim
38 words
The method of claim 14 further comprising the steps of adjusting the output data strobe signal so that a transition of the output data strobe signal is ninety (90) degrees out-of-phase with a start of the data output.
Claim 21
Dependent Claim
21 words
The method of claim 14 further comprising the step of inhibiting the output of the echo clock signal during non-read operations.
Claim 22
Dependent Claim
27 words
The method of claim 14 wherein the output data is read from the synchronous memory device in response to a rising transition of the echo clock signal.
Claim 23
Dependent Claim
27 words
The method of claim 14 wherein the output data is read from the synchronous memory device in response to a falling transition of the echo clock signal.
Claim 24
Dependent Claim
30 words
The method of claim 14 wherein the output data is read from the synchronous memory device in response to a both rising and falling transitions of the echo clock signal.
Claim 25
Independent Claim
85 words
A method of reading data from a synchronous memory device, the method comprising the steps of: providing a clock signal to the synchronous memory device; initiating a memory read operation; generating an echo clock signal which has a frequency of n-times a frequency of the clock signal; outputting the echo clock signal from the synchronous memory device; monitoring the echo clock signal with an external processor; and reading data output from the synchronous memory device in response to a transition of the echo clock signal.
Claim 26
Independent Claim
85 words
A method of reading data from a synchronous memory device, the method comprising the steps of: providing a clock signal to the synchronous memory device; initiating a memory read operation; generating an echo clock signal which has a frequency of n-times a frequency of the clock signal; outputting the echo clock signal from the synchronous memory device; monitoring the echo clock signal with an external processor; and reading data output from the synchronous memory device in response to a transition of the echo clock signal.
Claim 27
Dependent Claim
74 words
A synchronous memory device comprising: an input for receiving a clock signal; an output for providing an echo clock signal which substantially follows the clock signal during a data read operation, the echo clock signal having a frequency which is higher than a frequency of the clock signal and transitions of the echo clock signal indicate when data is available on data output lines; and a generating circuit for producing the output strobe signal.
Claim 28
Dependent Claim
74 words
A synchronous memory device comprising: an input for receiving a clock signal; an output for providing an echo clock signal which substantially follows the clock signal during a data read operation, the echo clock signal having a frequency which is higher than a frequency of the clock signal and transitions of the echo clock signal indicate when data is available on data output lines; and a generating circuit for producing the output strobe signal.
Claim 29
Dependent Claim
22 words
The synchronous memory device of claim 22 wherein the echo clock signal also substantially follows the clock signal during non-data read operations.
Claim 30
Dependent Claim
29 words
The synchronous memory device of claim 22 wherein either a rising or falling transition of the echo clock signal indicates that data is available on the data output lines.
Claim 31
Dependent Claim
23 words
The synchronous memory device of claim 22 wherein the echo clock signal indicates a start of data transmission on the data output lines.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-22 | 2002-08-24 | 2003-02-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-22 | 2006-08-24 | 2007-02-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-22 | 2010-08-24 | 2011-02-23 | $7700.00 | Window Closed / Lapsed |