US5724288A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data communication for memory
Assignee: Round Rock Research LLC
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Filing: 1995-08-30
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Granted: 1998-03-03
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Expires: 2015-08-30
Abstract
Abstract A memory circuit is described which includes memory cells for storing data. The memory circuit can be read from or written to by an external system such as a microprocessor or core logic chip set. The microprocessor provides memory cell address data to the memory circuit and can request that data be output on communication lines for reading therefrom. The memory circuit reduces the time needed to read data stored in the memory by providing a valid output data signal. The valid output data signal indicates that data coupled to the communication lines has stabilized and is therefore valid. Different valid output data signals and trigger circuits for producing the signals are described.
Inventors
- 👤 Eugene H. Cloud
- 👤 Brett Williams
- 👤 Troy A. Manning
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:32
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C7/00; G11C7/10; G11C7/1051; G11C7/1063; G11C11/4076; G11C7/22
Claims Analysis
Total Claims: 57
Claim 1
Independent Claim
127 words
An integrated memory circuit comprising: randomly addressable memory cells for storing data; a plurality of data output lines; a buffer circuit for coupling the data stored in the randomly addressable memory cells to the plurality of data output lines in response to an external data request signal; and a trigger circuit which produces a signal indicating that the data coupled to the plurality of output data lines is valid; wherein the trigger circuit comprises: a pull-up circuit for selectively pulling the output data strobe signal high; a pull-down circuit for selectively pulling the output data strobe signal low; and an enable circuit coupled to the pull-up circuit and the pull-down circuit for activating either the pull-up circuit or the pull-down circuit in response to an external signal.
Claim 2
Dependent Claim
127 words
An integrated memory circuit comprising: randomly addressable memory cells for storing data; a plurality of data output lines; a buffer circuit for coupling the data stored in the randomly addressable memory cells to the plurality of data output lines in response to an external data request signal; and a trigger circuit which produces a signal indicating that the data coupled to the plurality of output data lines is valid; wherein the trigger circuit comprises: a pull-up circuit for selectively pulling the output data strobe signal high; a pull-down circuit for selectively pulling the output data strobe signal low; and an enable circuit coupled to the pull-up circuit and the pull-down circuit for activating either the pull-up circuit or the pull-down circuit in response to an external signal.
Claim 3
Dependent Claim
66 words
An integrated circuit memory comprising: memory cells for storing data; output communication means for outputting the data stored in the memory cells; and an output signal circuit for indicating that valid data is available from the output communication means; wherein the output signal circuit comprises: an output signal connection, and a trigger circuit coupled to the output signal connection for producing an output data strobe signal.
Claim 4
Dependent Claim
66 words
An integrated circuit memory comprising: memory cells for storing data; output communication means for outputting the data stored in the memory cells; and an output signal circuit for indicating that valid data is available from the output communication means; wherein the output signal circuit comprises: an output signal connection, and a trigger circuit coupled to the output signal connection for producing an output data strobe signal.
Claim 5
Dependent Claim
18 words
The integrated circuit memory of claim 2 wherein the output data strobe signal is an active low pulse.
Claim 6
Dependent Claim
18 words
The integrated circuit memory of claim 2 wherein the output data strobe signal is an active high pulse.
Claim 7
Dependent Claim
24 words
The integrated circuit memory of claim 2 wherein the output data strobe signal toggles when valid data is available from the output communication means.
Claim 8
Dependent Claim
65 words
The integrated circuit memory of claim 2 wherein the trigger circuit comprises: a pull-up circuit for selectively pulling the output data strobe signal high; a pull-down circuit for selectively pulling the output data strobe signal low; and an enable circuit coupled to the pull-up circuit and the pull-down circuit for activating either the pull-up circuit or the pull-down circuit in response to an external signal.
Claim 9
Dependent Claim
57 words
The integrated circuit memory of claim 2 wherein the trigger circuit comprises; a pull-up circuit for selectively pulling the output data strobe signal high; a pull-down circuit for selectively pulling the output data strobe signal low; and an enable circuit for activating either the pull-up circuit or the pull-down circuit in response to the output communication means.
Claim 10
Dependent Claim
44 words
The integrated circuit memory of claim 2 wherein the trigger circuit comprises: a pull-up circuit for selectively pulling the output data strobe signal high; and an enable circuit coupled to the pull-up circuit for activating the pull-up circuit in response to an external signal.
Claim 11
Dependent Claim
44 words
The integrated circuit memory of claim 2 wherein the trigger circuit comprises: a pull-down circuit for selectively pulling the output data strobe signal low; and an enable circuit coupled to the pull-down circuit for activating the pull-down circuit in response to an external signal.
Claim 12
Dependent Claim
86 words
An integrated memory circuit comprising: randomly addressable memory cells for storing data; a plurality of data output lines; a buffer circuit for coupling the data stored in the randomly addressable memory cells to the plurality, of data output lines in response to an external data request signal; and a trigger circuit which produces a signal indicating that the data coupled to the plurality of output data lines is valid; wherein the signal toggles when the data coupled to the plurality of output data lines is valid.
Claim 13
Dependent Claim
86 words
An integrated memory circuit comprising: randomly addressable memory cells for storing data; a plurality of data output lines; a buffer circuit for coupling the data stored in the randomly addressable memory cells to the plurality, of data output lines in response to an external data request signal; and a trigger circuit which produces a signal indicating that the data coupled to the plurality of output data lines is valid; wherein the signal toggles when the data coupled to the plurality of output data lines is valid.
Claim 14
Dependent Claim
20 words
The integrated circuit memory of claim 10 wherein the integrated circuit memory is a dynamic random access memory circuit (DRAM).
Claim 15
Dependent Claim
20 words
The integrated circuit memory of claim 10 wherein the integrated circuit memory is a static random access memory circuit (SRAM).
Claim 16
Dependent Claim
21 words
The integrated circuit memory of claim 10 wherein the integrated circuit memory is a synchronous dynamic random access memory circuit (SDRAM).
Claim 17
Dependent Claim
21 words
The integrated circuit memory of claim 10 wherein the integrated circuit memory is a synchronous static random access memory circuit (SSRAM).
Claim 18
Dependent Claim
29 words
The integrated circuit memory of claim 10 wherein the integrated circuit memory is a random access memory circuit (RAM) which operates as a burst extended data output (BEDO) memory.
Claim 19
Dependent Claim
30 words
The integrated circuit memory of claim 10 wherein the integrated circuit memory is a random access memory circuit (RAM) which operates as a clocked burst extended data output (BEDO) memory.
Claim 20
Dependent Claim
106 words
An integrated memory circuit comprising: randomly addressable memory cells for storing data; a plurality of data output lines; a buffer circuit for coupling the data stored in the randomly addressable memory cells to the plurality of data output lines in response to an external data request signal; and a trigger circuit which produces a signal indicating that the data coupled to the plurality of output data lines is valid; wherein the trigger circuit comprises: a pull-up circuit for selectively pulling the output data strobe signal high; and an enable circuit coupled to the pull-up circuit for activating the pull-up circuit in response to an external signal.
Claim 21
Dependent Claim
106 words
An integrated memory circuit comprising: randomly addressable memory cells for storing data; a plurality of data output lines; a buffer circuit for coupling the data stored in the randomly addressable memory cells to the plurality of data output lines in response to an external data request signal; and a trigger circuit which produces a signal indicating that the data coupled to the plurality of output data lines is valid; wherein the trigger circuit comprises: a pull-up circuit for selectively pulling the output data strobe signal high; and an enable circuit coupled to the pull-up circuit for activating the pull-up circuit in response to an external signal.
Claim 22
Dependent Claim
106 words
An integrated memory circuit comprising: randomly addressable memory cells for storing data; a plurality of data output lines; a buffer circuit for coupling the data stored in the randomly addressable memory cells to the plurality of data output lines in response to an external data request signal; and a trigger circuit which produces a signal indicating that the data coupled to the plurality of output data lines is valid; wherein the trigger circuit comprises: a pull-down circuit for selectively pulling the output data strobe signal low; and an enable circuit coupled to the pull-down circuit for activating the pull-down circuit in response to an external signal.
Claim 23
Dependent Claim
106 words
An integrated memory circuit comprising: randomly addressable memory cells for storing data; a plurality of data output lines; a buffer circuit for coupling the data stored in the randomly addressable memory cells to the plurality of data output lines in response to an external data request signal; and a trigger circuit which produces a signal indicating that the data coupled to the plurality of output data lines is valid; wherein the trigger circuit comprises: a pull-down circuit for selectively pulling the output data strobe signal low; and an enable circuit coupled to the pull-down circuit for activating the pull-down circuit in response to an external signal.
Claim 24
Dependent Claim
132 words
An integrated memory circuit comprising: randomly addressable memory cells for storing data; a plurality of data output lines; a buffer circuit for coupling the data stored in the randomly addressable memory cells to the plurality of data output lines in response to an external data request signal; and a trigger circuit which produces a signal indicating that the data coupled to the plurality of output data lines is valid; wherein the trigger circuit comprises: a pull-up circuit for selectively pulling the output data strobe signal high; a pull-down circuit for selectively pulling the output data strobe signal low; and an enable circuit coupled to the pull-up circuit and the pull-down circuit for activating either the pull-up circuit or the pull-down circuit in response to one of the plurality of data output lines.
Claim 25
Dependent Claim
132 words
An integrated memory circuit comprising: randomly addressable memory cells for storing data; a plurality of data output lines; a buffer circuit for coupling the data stored in the randomly addressable memory cells to the plurality of data output lines in response to an external data request signal; and a trigger circuit which produces a signal indicating that the data coupled to the plurality of output data lines is valid; wherein the trigger circuit comprises: a pull-up circuit for selectively pulling the output data strobe signal high; a pull-down circuit for selectively pulling the output data strobe signal low; and an enable circuit coupled to the pull-up circuit and the pull-down circuit for activating either the pull-up circuit or the pull-down circuit in response to one of the plurality of data output lines.
Claim 26
Dependent Claim
67 words
A memory comprising: input circuitry configured to receive at least one input signal and to provide an output signal in response; logic circuitry configured to receive the output signal and to receive an enable signal, the logic circuitry producing a gating signal in response to the output signal and the enable signal; and output circuitry configured to receive the gating signal to provide an output strobe signal.
Claim 27
Dependent Claim
67 words
A memory comprising: input circuitry configured to receive at least one input signal and to provide an output signal in response; logic circuitry configured to receive the output signal and to receive an enable signal, the logic circuitry producing a gating signal in response to the output signal and the enable signal; and output circuitry configured to receive the gating signal to provide an output strobe signal.
Claim 28
Dependent Claim
13 words
The memory of claim 20 wherein the input signal is a column-address-strobe signal.
Claim 29
Dependent Claim
13 words
The memory of claim 20, wherein the input signal is a clock signal.
Claim 30
Dependent Claim
14 words
The memory of claim 20, wherein the enable signal is an output enable signal.
Claim 31
Dependent Claim
70 words
A memory comprising: trigger circuitry configured to receive a pulsed input signal and to provide a pulsed output signal using the pulsed input signal; logic circuitry configured to receive the pulsed output signal and to receive an enable signal, the logic circuitry producing gating signals using the pulsed output signal and the enable signal; and output driver circuitry configured to receive the gating signals to provide an output strobe signal.
Claim 32
Dependent Claim
70 words
A memory comprising: trigger circuitry configured to receive a pulsed input signal and to provide a pulsed output signal using the pulsed input signal; logic circuitry configured to receive the pulsed output signal and to receive an enable signal, the logic circuitry producing gating signals using the pulsed output signal and the enable signal; and output driver circuitry configured to receive the gating signals to provide an output strobe signal.
Claim 33
Dependent Claim
14 words
The memory of claim 24, wherein the pulsed input signal is a column-address-strobe signal.
Claim 34
Dependent Claim
14 words
The memory of claim 24, wherein the pulsed input signal is a clock signal.
Claim 35
Dependent Claim
14 words
The memory of claim 24, wherein the pulsed input signal is a data signal.
Claim 36
Dependent Claim
14 words
The memory of claim 24, wherein the enable signal is an output enable signal.
Claim 37
Dependent Claim
22 words
The memory of claim 24, wherein the output strobe signal operates at a frequency different from that of the pulsed input signal.
Claim 38
Dependent Claim
72 words
A memory comprising: trigger circuitry configured to receive a control signal and a clock signal and to provide a clocked output signal therefrom; logic circuitry configured to receive the clocked output signal and to receive an enable signal, the logic circuitry configured to provide gating signals from the clocked output signal and the enable signal; and output driver circuitry configured to receive the gating signals to provide an output data strobe signal.
Claim 39
Dependent Claim
72 words
A memory comprising: trigger circuitry configured to receive a control signal and a clock signal and to provide a clocked output signal therefrom; logic circuitry configured to receive the clocked output signal and to receive an enable signal, the logic circuitry configured to provide gating signals from the clocked output signal and the enable signal; and output driver circuitry configured to receive the gating signals to provide an output data strobe signal.
Claim 40
Dependent Claim
18 words
The memory of claim 30, wherein the output data strobe signal is approximately synchronous with the clock signal.
Claim 41
Dependent Claim
17 words
The memory of claim 30, wherein the output data strobe signal is synchronized to the clock signal.
Claim 42
Dependent Claim
22 words
The memory of claim 32, wherein the output data strobe signal operates at a frequency different from that of the clock signal.
Claim 43
Dependent Claim
17 words
The memory of claim 32, wherein the output data strobe signal is provided contemporaneously with data signals.
Claim 44
Dependent Claim
19 words
The memory of claim 34, wherein the output data strobe signal is coincident with each of the data signals.
Claim 45
Dependent Claim
17 words
The memory of claim 35, wherein the output data strobe signal information is provided to a microprocessor.
Claim 46
Dependent Claim
73 words
A memory comprising: comparator having a reference signal input, a data signal input, and a signal output; a gate circuit having a first input coupled to the signal output and an enable signal input, the gate circuit having a gating signal output; and an output driver circuit having an input coupled to the gating signal output, the output driver circuit responsive to the gating signal output to provide an output data strobe signal.
Claim 47
Dependent Claim
73 words
A memory comprising: comparator having a reference signal input, a data signal input, and a signal output; a gate circuit having a first input coupled to the signal output and an enable signal input, the gate circuit having a gating signal output; and an output driver circuit having an input coupled to the gating signal output, the output driver circuit responsive to the gating signal output to provide an output data strobe signal.
Claim 48
Independent Claim
64 words
A method for reading a memory, the method comprising the steps of: receiving an input signal; generating an output signal in response to the input signal; receiving the output signal and an enable signal; providing a gating signal in response to the output signal and the enable signal; receiving the gating signal; and outputting a data strobe signal in response to the gating signal.
Claim 49
Independent Claim
64 words
A method for reading a memory, the method comprising the steps of: receiving an input signal; generating an output signal in response to the input signal; receiving the output signal and an enable signal; providing a gating signal in response to the output signal and the enable signal; receiving the gating signal; and outputting a data strobe signal in response to the gating signal.
Claim 50
Independent Claim
65 words
A method for reading a memory, the method comprising the steps of: receiving a control signal and a clock signal; generating an output signal using the control signal and the clock signal; receiving the output signal and an enable signal; providing gating signals using the output signal and the enable signal; receiving the gating signals; and outputting a data strobe signal using the gating signals.
Claim 51
Independent Claim
65 words
A method for reading a memory, the method comprising the steps of: receiving a control signal and a clock signal; generating an output signal using the control signal and the clock signal; receiving the output signal and an enable signal; providing gating signals using the output signal and the enable signal; receiving the gating signals; and outputting a data strobe signal using the gating signals.
Claim 52
Independent Claim
65 words
A method for reading a memory, the method comprising the steps of: receiving a control signal and a clock signal; generating an output signal using the control signal and the clock signal; receiving the output signal and an enable signal; outputting gating signals using the output signal and the enable signal; receiving the gating signals; and outputting a data strobe signal using the gating signals.
Claim 53
Independent Claim
65 words
A method for reading a memory, the method comprising the steps of: receiving a control signal and a clock signal; generating an output signal using the control signal and the clock signal; receiving the output signal and an enable signal; outputting gating signals using the output signal and the enable signal; receiving the gating signals; and outputting a data strobe signal using the gating signals.
Claim 54
Independent Claim
60 words
A method for accessing read data of a memory having an output line, the method comprising the steps of: providing the read data on the output line; generating a data strobe signal in response to the read data; and providing the data strobe signal off of the read data so as not to be limited by a predefined access time.
Claim 55
Independent Claim
60 words
A method for accessing read data of a memory having an output line, the method comprising the steps of: providing the read data on the output line; generating a data strobe signal in response to the read data; and providing the data strobe signal off of the read data so as not to be limited by a predefined access time.
Claim 56
Dependent Claim
18 words
The method of claim 41, wherein the data strobe signal is not frequency limited by a clock signal.
Claim 57
Dependent Claim
18 words
The method of claim 41, wherein the data strobe signal is synchronized to frequency of a clock signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-02 | 2001-09-01 | 2002-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-02 | 2005-09-01 | 2006-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-02 | 2009-09-01 | 2010-03-03 | $7700.00 | Window Closed / Lapsed |