Method and apparatus for memory sequencing

Claim 1

An apparatus for directing frames received asynchronously by a fibre channel port, synchronously into a receive memory, comprising: a data path coupling the fibre channel port and the receive memory, the data path further comprising a circular buffer for synchronizing passing of a frame to the receive memory and a sequencer coupled to the receive memory and the circular buffer for generating control signals to control output of the frame from the circular buffer to be in sequence with a memory clock cycle sequence of the receive memory, wherein the frame is store synchronously in the receive memory.

Claim 2

An apparatus for directing frames received asynchronously by a fibre channel port, synchronously into a receive memory, comprising: a data path coupling the fibre channel port and the receive memory, the data path further comprising a circular buffer for synchronizing passing of a frame to the receive memory and a sequencer coupled to the receive memory and the circular buffer for generating control signals to control output of the frame from the circular buffer to be in sequence with a memory clock cycle sequence of the receive memory, wherein the frame is store synchronously in the receive memory.

Claim 9

An apparatus for directing frames received asynchronously by a plurality of fibre channel ports identified as port 0, port 1, port 2 and port 3 into a receive memory synchronously, comprising: a data path coupling each fibre channel port and the receive memory, wherein the data path is two-bits wide and each frame is bit-sliced in port 0, port 1, port 2 and port 3; a circular buffer in the data path for synchronizing passing of a frame to the receive memory, the circular buffer further comprising an array of flip-flops, a write pointer for pointing to the flip-flop in which data is going to be stored, and a read pointer for pointing to the flip-flop from which data is to be read; an accumulator in the data path for accumulating data from the two-bit wide data path into 16-bit wide data for storage in the receive memory; a first sequencer located in a memory interface with three other sequencers and coupled to the receive memory and the circular buffer for generating control signals to control output of the frame from the circular buffer to be in sequence with a memory clock cycle sequence of the receive memory, wherein the frame is stored synchronously in the receive memory and the first sequencer is synchronized to a common system sync pulse to provide for storing the frame in the receive memory, wherein passing of data to the accumulator is synchronized by providing a read pulse to flip-flops in the array to coincide with the memory cycle sequence appropriate for writing frames into the receive memory: a port intelligence mechanism associated with each fibre channel port, wherein the first sequencer is aware of its position (0,1,2,3) in the memory interface relative to the three other sequencers and the first sequencer is aware of the baud rate of the port intelligence mechanism, wherein frames are stored in the circular buffer in the same distributed format regardless of port speed.

Claim 10

An apparatus for directing frames received asynchronously by a plurality of fibre channel ports identified as port 0, port 1, port 2 and port 3 into a receive memory synchronously, comprising: a data path coupling each fibre channel port and the receive memory, wherein the data path is two-bits wide and each frame is bit-sliced in port 0, port 1, port 2 and port 3; a circular buffer in the data path for synchronizing passing of a frame to the receive memory, the circular buffer further comprising an array of flip-flops, a write pointer for pointing to the flip-flop in which data is going to be stored, and a read pointer for pointing to the flip-flop from which data is to be read; an accumulator in the data path for accumulating data from the two-bit wide data path into 16-bit wide data for storage in the receive memory; a first sequencer located in a memory interface with three other sequencers and coupled to the receive memory and the circular buffer for generating control signals to control output of the frame from the circular buffer to be in sequence with a memory clock cycle sequence of the receive memory, wherein the frame is stored synchronously in the receive memory and the first sequencer is synchronized to a common system sync pulse to provide for storing the frame in the receive memory, wherein passing of data to the accumulator is synchronized by providing a read pulse to flip-flops in the array to coincide with the memory cycle sequence appropriate for writing frames into the receive memory: a port intelligence mechanism associated with each fibre channel port, wherein the first sequencer is aware of its position (0,1,2,3) in the memory interface relative to the three other sequencers and the first sequencer is aware of the baud rate of the port intelligence mechanism, wherein frames are stored in the circular buffer in the same distributed format regardless of port speed.

Claim 16

A method for directing frames received asynchronously by a fibre channel port, synchronously into a receive memory, comprising the method steps of: coupling the fibre channel port to the receive memory over a data path, the data path further comprising a circular buffer, temporarily storing a frame in the circular buffer, sychronizing the passing of the frame from the circular buffer to the receive memory to coincide with a memory clock cycle sequence of the receive memory, wherein the frame is stored sychronously in the receive memory.

Claim 17

A method for directing frames received asynchronously by a fibre channel port, synchronously into a receive memory, comprising the method steps of: coupling the fibre channel port to the receive memory over a data path, the data path further comprising a circular buffer, temporarily storing a frame in the circular buffer, sychronizing the passing of the frame from the circular buffer to the receive memory to coincide with a memory clock cycle sequence of the receive memory, wherein the frame is stored sychronously in the receive memory.