US5452010A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Synchronizing digital video inputs
Assignee: Grass Valley USA LLC
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Filing: 1994-07-18
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Granted: 1995-09-19
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Expires: 2014-07-18
Abstract
Abstract A system for synchronizing asynchronous video signals with a reference signal for input to a digital video processing system has a first-in, first-out (FIFO) buffer for each input signal that writes the digitized video signal into the FIFO under control of an input clock signal derived from the digitized video signal, and reads the digitized video signal from the FIFO under control of the reference signal. An input state machine monitors the digitized video signal at the input and the occupancy of the FIFO to provide a write enable signal to the FIFO so long as the FIFO is not in danger of overflowing. An output state machine monitors the digitized video signal at the output and the occupancy of the FIFO to provide a read enable signal to the FIFO so long as the FIFO is not in danger of underflowing. When the FIFO is in danger of overflowing, the write enable signal is disabled during the blanking interval of the digitized video signal for a pre-determined number of pixels; and when the FIFO is in danger of underflowing, the read enable signal is disabled during the blanking interval of the digitized video signal for a pre-determined number of pixels.
Inventors
- 👤 Douglas J. Doornink
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:43
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/06; H04N5/067; H04N5/073
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
241 words
An apparatus for synchronizing a digital video signal at a first clock rate with a reference clock rate comprising: a buffer for storing the digital video signal at the first clock rate when enabled by a write enable signal and for outputting the digital video signal at the reference clock rate when enabled by a read enable signal; an input state machine for generating the write enable signal in response to the digital video signal being stored in the buffer, a high threshold signal from the buffer having a state indicating occupancy of the buffer, and the first clock rate; and an output state machine for generating the read enable signal in response to the digital video signal being output from the buffer, a low threshold signal from the buffer having a state indicating occupancy of the buffer, and the reference clock rate; such that if the state of the high threshold signal indicates that the buffer is in danger of overflowing, the write enable signal is inhibited during a blanking interval of the digital video signal being stored in the buffer for a first predetermined number of pixels of the digital video signal, and if the low threshold signal indicates that the buffer is in danger of underflowing, the read enable signal is inhibited during a blanking interval of the digital video signal being output from the buffer for a second predetermined number of pixels of the digital video signal.
Claim 2
Independent Claim
241 words
An apparatus for synchronizing a digital video signal at a first clock rate with a reference clock rate comprising: a buffer for storing the digital video signal at the first clock rate when enabled by a write enable signal and for outputting the digital video signal at the reference clock rate when enabled by a read enable signal; an input state machine for generating the write enable signal in response to the digital video signal being stored in the buffer, a high threshold signal from the buffer having a state indicating occupancy of the buffer, and the first clock rate; and an output state machine for generating the read enable signal in response to the digital video signal being output from the buffer, a low threshold signal from the buffer having a state indicating occupancy of the buffer, and the reference clock rate; such that if the state of the high threshold signal indicates that the buffer is in danger of overflowing, the write enable signal is inhibited during a blanking interval of the digital video signal being stored in the buffer for a first predetermined number of pixels of the digital video signal, and if the low threshold signal indicates that the buffer is in danger of underflowing, the read enable signal is inhibited during a blanking interval of the digital video signal being output from the buffer for a second predetermined number of pixels of the digital video signal.
Claim 3
Independent Claim
264 words
An apparatus for synchronizing a digital video signal at a first clock rate with a reference clock rate comprising: means for storing the digital video signal at the first clock rate when enabled by a write enable signal and for outputting the digital video signal at the reference clock rate when enabled by a read enable signal; means for generating the write enable signal in response to the digital video signal being stored in the storing and outputting means, a high threshold signal from the storing and outputting means having a state indicating occupancy of the storing and outputting means, and the first clock rate; and means for generating the read enable signal in response to the digital video signal being output from the storing and outputting means, a low threshold signal from the storing and outputting means having a state indicating occupancy of the storing and outputting means, and the reference clock rate; such that if the state of the high threshold signal indicates that the storing and outputting means is in danger of overflowing, the write enable signal is inhibited during a blanking interval of the digital video signal being stored in the storing and outputting means for a first predetermined number of pixels of the digital video signal, and if the low threshold signal indicates that the storing and outputting means is in danger of underflowing, the read enable signal is inhibited during a blanking interval of the digital video signal being output from the storing and outputting means for a second predetermined number of pixels of the digital video signal.
Claim 4
Independent Claim
264 words
An apparatus for synchronizing a digital video signal at a first clock rate with a reference clock rate comprising: means for storing the digital video signal at the first clock rate when enabled by a write enable signal and for outputting the digital video signal at the reference clock rate when enabled by a read enable signal; means for generating the write enable signal in response to the digital video signal being stored in the storing and outputting means, a high threshold signal from the storing and outputting means having a state indicating occupancy of the storing and outputting means, and the first clock rate; and means for generating the read enable signal in response to the digital video signal being output from the storing and outputting means, a low threshold signal from the storing and outputting means having a state indicating occupancy of the storing and outputting means, and the reference clock rate; such that if the state of the high threshold signal indicates that the storing and outputting means is in danger of overflowing, the write enable signal is inhibited during a blanking interval of the digital video signal being stored in the storing and outputting means for a first predetermined number of pixels of the digital video signal, and if the low threshold signal indicates that the storing and outputting means is in danger of underflowing, the read enable signal is inhibited during a blanking interval of the digital video signal being output from the storing and outputting means for a second predetermined number of pixels of the digital video signal.
Claim 5
Independent Claim
213 words
A method of synchronizing a digital video signal with a reference signal having a system clock rate comprising the steps of: writing the digital video signal into a buffer when enabled by a write enable signal at an input clock rate, the input clock rate being derived from the digital video signal; reading the digital video signal from the buffer when enabled by a read enable signal at the system clock rate; generating the write enable signal from the digital video signal being written into the buffer, from a high threshold signal having a state indicating occupancy of the buffer, and from the input clock rate so that the write enable signal is disabled for a first pre-determined number of pixels of the digital video signal when the state of the high threshold signal indicates the buffer is in danger of overflowing; and generating the read enable signal from the digital video signal being read from the buffer, from a low threshold signal having a state indicating occupancy of the buffer, and from the system clock rate so that the read enable signal is disabled for a second pre-determined number of pixels of the digital video signal when the state of the low threshold signal indicates the buffer is in danger of underflowing.
Claim 6
Independent Claim
213 words
A method of synchronizing a digital video signal with a reference signal having a system clock rate comprising the steps of: writing the digital video signal into a buffer when enabled by a write enable signal at an input clock rate, the input clock rate being derived from the digital video signal; reading the digital video signal from the buffer when enabled by a read enable signal at the system clock rate; generating the write enable signal from the digital video signal being written into the buffer, from a high threshold signal having a state indicating occupancy of the buffer, and from the input clock rate so that the write enable signal is disabled for a first pre-determined number of pixels of the digital video signal when the state of the high threshold signal indicates the buffer is in danger of overflowing; and generating the read enable signal from the digital video signal being read from the buffer, from a low threshold signal having a state indicating occupancy of the buffer, and from the system clock rate so that the read enable signal is disabled for a second pre-determined number of pixels of the digital video signal when the state of the low threshold signal indicates the buffer is in danger of underflowing.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-18 | 1999-03-20 | 1999-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-18 | 2003-03-20 | 2003-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-18 | 2007-03-20 | 2007-09-19 | $7700.00 | Window Closed / Lapsed |