Patent US5872719A successfully refreshed from Google Patents.
US5872719A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of wiring semiconductor integrated circuit and semiconductor integrated circuit
Assignee: Hitachi Ltd
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Filing: 1996-08-02
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Granted: 1999-02-16
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Expires: 2016-08-02
Abstract
Abstract In designing wiring for semiconductor integrated circuits, wiring channels are assigned to reduce a signal delay time developed parallel traces. The selection of the wiring channels for all of the wiring oriented nets of the circuits is based on the trunk trace length between the terminals. For the longer trunk trace lengths, a double-pitch wiring channel is assigned. First, the determined trunk-trace lengths are sorted in decreasing order of length. Then, a double-pitch wiring channel is assigned for the trunk-trace lengths that are greater than a predetermined length. When no double pitch channels remain, single pitch channels are used.
Inventors
- 👤 Yoshiaki Miyazaki
- 👤 Katsuyoshi Suzuki
- 👤 Naoki Kato
- 👤 Hiromitsu Yamada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 19:28
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/394
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
78 words
A method of designing wiring layout for a semiconductor integrated circuit, comprising the steps of: estimating wiring lengths of trunk traces between terminals in wiring oriented nets of said circuit; allocating first wiring channels having a predetermined minimum wiring interval and allocating second wiring channels having a pitch at least twice that of said predetermined wiring interval for each of said trunk traces on the basis of the lengths of said trunk traces determined in said estimating step.
Claim 2
Independent Claim
78 words
A method of designing wiring layout for a semiconductor integrated circuit, comprising the steps of: estimating wiring lengths of trunk traces between terminals in wiring oriented nets of said circuit; allocating first wiring channels having a predetermined minimum wiring interval and allocating second wiring channels having a pitch at least twice that of said predetermined wiring interval for each of said trunk traces on the basis of the lengths of said trunk traces determined in said estimating step.
Claim 3
Dependent Claim
44 words
A method according to claim 1, further including sorting said trunk traces according to said trunk trace lengths from longest to shortest and allocating said second wiring channels to said trunk traces in decreasing order from said longest to said shortest trunk trace lengths.
Claim 4
Dependent Claim
75 words
A method according to claim 1, further including sorting said trunk traces according to said wiring lengths of said trunk traces by comparing said wiring lengths to a predetermined reference value; and assigning said second channels to said trunk traces having said trunk trace lengths that exceed said reference value in decreasing order beginning with ones of said trunk traces having a trunk trace length that is determined to be a longest trunk trace length.
Claim 5
Dependent Claim
22 words
A method according to claim 3, wherein said reference value is determined to be about 60% of said longest trunk trace length.
Claim 6
Dependent Claim
40 words
A method according to claim 3, further including assigning said second channels to said trunk traces determined to exceed said reference value until said second channels have been exhausted, and then assigning said first channels to the remaining trunk traces.
Claim 7
Dependent Claim
24 words
A method according to claim 1, wherein said second wiring channels have a pitch equal to twice that of said predetermined minimum wiring interval.
Claim 8
Independent Claim
73 words
A method of designing wiring layout for a semiconductor integrated circuit, comprising the steps of: allocating parallel trunk traces between terminals for elements of adjacent nets of said circuit; determining a parallel wiring-length limiting value that limits the length of the parallel trunk traces according to a drive capability of said elements of said adjacent nets; and limiting the length of a parallel trunk trace in accordance with said parallel wiring-length limiting value.
Claim 9
Independent Claim
73 words
A method of designing wiring layout for a semiconductor integrated circuit, comprising the steps of: allocating parallel trunk traces between terminals for elements of adjacent nets of said circuit; determining a parallel wiring-length limiting value that limits the length of the parallel trunk traces according to a drive capability of said elements of said adjacent nets; and limiting the length of a parallel trunk trace in accordance with said parallel wiring-length limiting value.
Claim 10
Independent Claim
67 words
A method of designing wiring layout for a semiconductor integrated circuit, comprising the steps of: allocating parallel trunk traces between terminals for sources and gates, respectively, of adjacent nets of said circuit; limiting the length of a parallel trunk trace in the connection between one of said sources and said gates according to a distance that said parallel trunk trace is spaced apart from said one source.
Claim 11
Independent Claim
67 words
A method of designing wiring layout for a semiconductor integrated circuit, comprising the steps of: allocating parallel trunk traces between terminals for sources and gates, respectively, of adjacent nets of said circuit; limiting the length of a parallel trunk trace in the connection between one of said sources and said gates according to a distance that said parallel trunk trace is spaced apart from said one source.
Claim 12
Dependent Claim
36 words
A method according to claim 8, wherein said length of said parallel trunk trace is limited according to the drive capability of the source-to-gate drive capability for the connection between said one source and said gates.
Claim 13
Dependent Claim
19 words
A method according to claim 8, wherein said parallel trunk trace is limited as said spaced apart distance increases.
Claim 14
Dependent Claim
83 words
A program stored on a computer readable storage medium for designing a wiring layout for a semiconductor integrated circuit, comprising: estimating wiring lengths of trunk traces between terminals in wiring oriented nets of said circuit; allocating first wiring channels having a predetermined minimum wiring interval and allocating second wiring channels having a pitch at least twice that of said predetermined wiring interval for each of said trunk traces on the basis of the lengths of said trunk traces determined in said estimating step.
Claim 15
Dependent Claim
83 words
A program stored on a computer readable storage medium for designing a wiring layout for a semiconductor integrated circuit, comprising: estimating wiring lengths of trunk traces between terminals in wiring oriented nets of said circuit; allocating first wiring channels having a predetermined minimum wiring interval and allocating second wiring channels having a pitch at least twice that of said predetermined wiring interval for each of said trunk traces on the basis of the lengths of said trunk traces determined in said estimating step.
Claim 16
Dependent Claim
44 words
A program according to claim 11, further including sorting said trunk traces according to said trunk trace lengths from longest to shortest and allocating said second wiring channels to said trunk traces in decreasing order from said longest to said shortest trunk trace lengths.
Claim 17
Dependent Claim
75 words
A program according to claim 11, further including sorting said trunk traces according to said wiring lengths of said trunk traces by comparing said wiring lengths to a predetermined reference value; and assigning said second channels to said trunk traces having said trunk trace lengths that exceed said reference value in decreasing order beginning with ones of said trunk traces having a trunk trace length that is determined to be a longest trunk trace length.
Claim 18
Dependent Claim
22 words
A program according to claim 13, wherein said reference value is determined to be about 60% of said longest trunk trace length.
Claim 19
Dependent Claim
86 words
A computer readable storage medium encoded with executable instructions representing a program for designing a wiring layout for a semiconductor integrated circuit, comprising: estimating wiring lengths of trunk traces between terminals in wiring oriented nets of said circuit; allocating first wiring channels having a predetermined minimum wiring interval and allocating second wiring channels having a pitch at least twice that of said predetermined wiring interval for each of said trunk traces on the basis of the lengths of said trunk traces determined in said estimating step.
Claim 20
Dependent Claim
86 words
A computer readable storage medium encoded with executable instructions representing a program for designing a wiring layout for a semiconductor integrated circuit, comprising: estimating wiring lengths of trunk traces between terminals in wiring oriented nets of said circuit; allocating first wiring channels having a predetermined minimum wiring interval and allocating second wiring channels having a pitch at least twice that of said predetermined wiring interval for each of said trunk traces on the basis of the lengths of said trunk traces determined in said estimating step.
Claim 21
Dependent Claim
47 words
A computer readable storage medium according to claim 15, further including sorting said trunk traces according to said trunk trace lengths from longest to shortest and allocating said second wiring channels to said trunk traces in decreasing order from said longest to said shortest trunk trace lengths.
Claim 22
Dependent Claim
78 words
A computer readable storage medium according to claim 15, further including sorting said trunk traces according to said wiring lengths of said trunk traces by comparing said wiring lengths to a predetermined reference value; and assigning said second channels to said trunk traces having said trunk trace lengths that exceed said reference value in decreasing order beginning with ones of said trunk traces having a trunk trace length that is determined to be a longest trunk trace length.
Claim 23
Dependent Claim
25 words
A computer readable storage medium according to claim 17, wherein said reference value is determined to be about 60% of said longest trunk trace length.
Claim 24
Dependent Claim
81 words
A computer readable storage medium encoded with executable instructions representing a program for designing a wiring layout for a semiconductor integrated circuit, comprising: allocating parallel trunk traces between terminals for elements of adjacent nets of said circuit; determining a parallel wiring-length limiting value that limits the length of the parallel trunk traces according to a drive capability of said elements of said adjacent nets; and limiting the length of a parallel trunk trace in accordance with said parallel wiring-length limiting value.
Claim 25
Dependent Claim
81 words
A computer readable storage medium encoded with executable instructions representing a program for designing a wiring layout for a semiconductor integrated circuit, comprising: allocating parallel trunk traces between terminals for elements of adjacent nets of said circuit; determining a parallel wiring-length limiting value that limits the length of the parallel trunk traces according to a drive capability of said elements of said adjacent nets; and limiting the length of a parallel trunk trace in accordance with said parallel wiring-length limiting value.
Claim 26
Dependent Claim
72 words
A program stored on a computer readable storage medium for designing a wiring layout for a semiconductor integrated circuit, comprising: allocating parallel trunk traces between terminals for sources and gates, respectively, of adjacent nets of said circuit; limiting the length of a parallel trunk trace in the connection between one of said sources and said gates according to a distance that said parallel trunk trace is spaced apart from said one source.
Claim 27
Dependent Claim
72 words
A program stored on a computer readable storage medium for designing a wiring layout for a semiconductor integrated circuit, comprising: allocating parallel trunk traces between terminals for sources and gates, respectively, of adjacent nets of said circuit; limiting the length of a parallel trunk trace in the connection between one of said sources and said gates according to a distance that said parallel trunk trace is spaced apart from said one source.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-15 | 2002-08-17 | 2003-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-15 | 2006-08-17 | 2007-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-15 | 2010-08-17 | 2011-02-16 | $7700.00 | Window Closed / Lapsed |