Nitrogenated gate structure for improved transistor performance and method for making same

Abstract

Abstract An integrated circuit fabrication method incorporating nitrogen into the polysilicon-dielectric interface in an MOS transistor. A semiconductor substrate having a P-well region and an N-well region is provided. Each well region includes channel regions and source/drain regions. A dielectric layer, preferably a thermal oxide, is formed on an upper surface of the semiconductor substrate. The thermal oxide can be grown in a nitrogen bearing ambient, an O 2 ambient, or an H 2 O ambient. Alternatively, the dielectric may be formed from a deposited oxide. Thereafter, a layer of polysilicon is formed on the dielectric layer and a plurality of "nitrogenated" polysilicon gates is formed on the dielectric layer over the channel regions. In a presently preferred embodiment, nitrogen species are introduced into the polysilicon gates with an ion implantation step. The nitrogen implantation step may alternatively be performed before or after the patterning of the polysilicon layer. If implantation occurs after patterning of the polysilicon layer, nitrogen will be introduced into the source/drain regions and effect an increase in drive current without a corresponding increase in leakage current. In a presently preferred embodiment, a dose of between 5×10 13 cm -2 and 1×10 16 cm -2 is used for implanting the nitrogen bearing species and the species is distributed within the plurality of polysilicon gates such that the concentration of the nitrogen is greatest at approximately a midpoint within said gates. The semiconductor substrate may be subsequently annealed in an ambient maintained between approximately 900° to 1100° C. preferably using a rapid thermal anneal apparatus.

Inventors

• 👤 Mark I. Gardner
• 👤 H. Jim Fulford, Jr.

Bibliographic Details