Enhanced ASIC process cell

Claim 2

A DRAM bit storage cell comprising a pair of capacitors each having one plate connected to a source or drain of a pass FET, another plate of a first of the pair of capacitors of similar type connected to a first fixed voltage rail or a fixed voltage rail larger in magnitude than the first voltage rail, and another plate of a second of the pair of capacitors connected to a second fixed voltage rail opposite in polarity to the first voltage rail.

Claim 3

A DRAM cell as defined in claim 1 in which the one plate of both capacitors of the pair of capacitors being common.

Claim 4

A DRAM bit storage cell comprising a pair of capacitors each having one plate connected to a source or drain of a pass FET, another plate of a first of the pair of capacitors connected to a first voltage rail or a fixed voltage rail larger in magnitude than the voltage of the first voltage rail, and another plate of a second of the pair of capacitors connected to a second fixed voltage rail opposite in polarity to the first voltage rail, the one plate of both capacitors of the pair of capacitors being common, the common plate comprising an insulated gate electrode of an FET capacitor.

Claim 5

A DRAM bit storage cell comprising a pair of capacitors each having one plate connected to a source or drain of a pass FET, another plate of a first of the pair of capacitors connected to a first voltage rail or a fixed voltage rail larger in magnitude than the voltage of the first voltage rail, and another plate of a second of the pair of capacitors connected to a second fixed voltage rail opposite in polarity to the first voltage rail, the one plate of both capacitors of the pair of capacitors being common, the common plate comprising an insulated gate electrode of an FET capacitor.

Claim 6

A DRAM cell as defined in claim 3 in which the gate electrode is formed of a first layer of polysilicon, and in which the another plate of the second of the pair of capacitors is formed of a second layer of polysilicon insulated from, and overlying, the first layer of polysilicon.

Claim 7

A DRAM bit storage circuit comprising a bit line for selectively receiving a bit line precharge voltage and a word line for selectively receiving a first voltage from a first voltage source, a cell access FET having a gate connected to the word line, a source or drain connected to the bit line, and another of the source or drain connected to a first plate of a first capacitor, a second plate of the first capacitor connected to a second fixed voltage source having similar polarity as the first voltage source, and a second capacitor of similar type as the first capacitor connected between the first plate of the first capacitor and a third fixed voltage source having polarity opposite to the first voltage source.

Claim 8

A DRAM bit storage circuit comprising a bit line for selectively receiving a bit line precharge voltage and a word line for selectively receiving a first voltage from a first voltage source, a cell access FET having a gate connected to the word line, a source or drain connected to the bit line, and another of the source or drain connected to a first plate of a first capacitor, a second plate of the first capacitor connected to a second fixed voltage source having similar polarity as the first voltage source, and a second capacitor of similar type as the first capacitor connected between the first plate of the first capacitor and a third fixed voltage source having polarity opposite to the first voltage source.

Claim 9

A DRAM bit storage circuit comprising a bit line for selectively receiving a bit line precharge voltage and a word line for selectively receiving a first voltage from a first voltage source, a cell access FET having a gate connected to the word line, a source or drain connected to the bit line, and another of the source or drain connected to a first plate of a first capacitor, a second plate of the first capacitor connected to a second voltage source having similar polarity as the first voltage source, and a second capacitor connected between the first plate of the first capacitor and a third voltage source having polarity opposite to the first voltage source the second capacitor having approximately similar capacitance as the first capacitor.

Claim 10

A DRAM bit storage circuit comprising a bit line for selectively receiving a bit line precharge voltage and a word line for selectively receiving a first voltage from a first voltage source, a cell access FET having a gate connected to the word line, a source or drain connected to the bit line, and another of the source or drain connected to a first plate of a first capacitor, a second plate of the first capacitor connected to a second voltage source having similar polarity as the first voltage source, and a second capacitor connected between the first plate of the first capacitor and a third voltage source having polarity opposite to the first voltage source the second capacitor having approximately similar capacitance as the first capacitor.

Claim 11

A DRAM circuit as defined in claim 6 in which a plate of the second capacitor other than the plate connected to the third voltage source is a common plate with the first plate of the first capacitor.

Claim 12

A DRAM circuit as defined in claim 7 in which the common plate of the first and second capacitors are comprised of a polysilicon gate of an FET which gate is short circuited to a source or drain of the FET, and in which another plate of the second capacitor is comprised of a polysilicon layer spaced and insulated from the polysilicon gate.

Claim 13

A DRAM circuit as defined in claim 7 in which the FET is p-channel type, the first voltage source has voltage Vdd, the voltage applied to the another plate of the first capacitor is Vdd or voltage Vpp which is boosted from Vdd by Vtn, and the third voltage source has voltage Vss, where Vtn is the operation threshold voltage of an n-channel FET.

Claim 14

A DRAM circuit as defined in claim 7 in which the FET is n-channel type, the first voltage source has voltage Vss, the voltage applied to the another plate of the first capacitor is Vss or a voltage which is Vss-Vtp, and the third voltage source has voltage Vdd, where voltage Vtp is the operation threshold voltage of a p-channel FET.

Claim 15

A DRAM circuit as defined in claim 7, in which the second capacitor is overlaid onto or stacked on top of the first capacitor.

Claim 16

A DRAM bit storage cell comprising a pair of serially connected capacitors forming a capacitor voltage divider, having a junction connected to a source or drain of a pass FET, a charge storage capacitor of the pair of capacitors having a plate connected to a first voltage rail or to a source of voltage boosted from the voltage of the first voltage rail, and a plate of the other of the pair of capacitors connected to a voltage rail having a voltage of a value such as to cause the voltage at said junction to be approximately half the voltage of the first voltage rail or half the boosted voltage.

Claim 17

A DRAM bit storage cell comprising a pair of serially connected capacitors forming a capacitor voltage divider, having a junction connected to a source or drain of a pass FET, a charge storage capacitor of the pair of capacitors having a plate connected to a first voltage rail or to a source of voltage boosted from the voltage of the first voltage rail, and a plate of the other of the pair of capacitors connected to a voltage rail having a voltage of a value such as to cause the voltage at said junction to be approximately half the voltage of the first voltage rail or half the boosted voltage.

Claim 18

A DRAM cell as defined in claim 12 in which plates of the capacitors which are connected at the junction are common.

Claim 19

An integrated circuit memory comprising, for each of plural charge storage cells, a first p-channel FET comprising a spaced pair of p+ type regions diffused or implanted into an n- type well of a p-type substrate and a first polysilicon gate overlying and insulated from a channel region adjacent to a surface of the n-type well between the spaced pair of p+ type regions, a polysilicon plate overlying and insulated from the polysilicon gate, a second p-channel FET having a third p+ type region diffused or implanted into the n-type well, a second polysilicon gate overlying and insulated from a channel region adjacent to a surface of the n-type well between the third p+ type region and one of the pair of p+ type regions, the first polysilicon gate being connected to the one of the pair of p+ type regions, the polysilicon plate being connected to a voltage source Vss, the second polysilicon gate being connected to a word line, the third p+ type region being connected to a bit line, and another of the pair of p+ type regions being connected to a source of Vdd or Vpp voltage.

Claim 20

An integrated circuit memory comprising, for each of plural charge storage cells, a first p-channel FET comprising a spaced pair of p+ type regions diffused or implanted into an n- type well of a p-type substrate and a first polysilicon gate overlying and insulated from a channel region adjacent to a surface of the n-type well between the spaced pair of p+ type regions, a polysilicon plate overlying and insulated from the polysilicon gate, a second p-channel FET having a third p+ type region diffused or implanted into the n-type well, a second polysilicon gate overlying and insulated from a channel region adjacent to a surface of the n-type well between the third p+ type region and one of the pair of p+ type regions, the first polysilicon gate being connected to the one of the pair of p+ type regions, the polysilicon plate being connected to a voltage source Vss, the second polysilicon gate being connected to a word line, the third p+ type region being connected to a bit line, and another of the pair of p+ type regions being connected to a source of Vdd or Vpp voltage.

Claim 21

An integrated circuit memory comprising, for each of plural charge storage cells, a first n-channel FET comprising a spaced pair of n+ type regions diffused into an p- type well contained in an n-type well in a p-type substrate substrate and a first polysilicon gate overlying and insulated from a channel region adjacent to a surface of the substrate between the spaced pair of n+ type regions, a polysilicon plate overlying and insulated from the polysilicon gate, a second n-channel FET having a third n+ type region diffused into the p-type well, a second polysilicon gate overlying and insulated from a channel region adjacent a surface of the substrate between the third n+ type region and one of the pair of n+ type regions, the first polysilicon gate being connected to the one of the pair of n+ type regions, the polysilicon plate being connected to a voltage source Vdd or Vpp, the second polysilicon gate being connected to a word line, the third n+ type region being connected to a bit line, and another of the pair of n+ type regions being connected to a voltage source of Vss.

Claim 22

An integrated circuit memory comprising, for each of plural charge storage cells, a first n-channel FET comprising a spaced pair of n+ type regions diffused into an p- type well contained in an n-type well in a p-type substrate substrate and a first polysilicon gate overlying and insulated from a channel region adjacent to a surface of the substrate between the spaced pair of n+ type regions, a polysilicon plate overlying and insulated from the polysilicon gate, a second n-channel FET having a third n+ type region diffused into the p-type well, a second polysilicon gate overlying and insulated from a channel region adjacent a surface of the substrate between the third n+ type region and one of the pair of n+ type regions, the first polysilicon gate being connected to the one of the pair of n+ type regions, the polysilicon plate being connected to a voltage source Vdd or Vpp, the second polysilicon gate being connected to a word line, the third n+ type region being connected to a bit line, and another of the pair of n+ type regions being connected to a voltage source of Vss.