Patent US5869879A successfully refreshed from Google Patents.
US5869879A
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CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions
Assignee: Advanced Micro Devices Inc
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Filing: 1996-12-06
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Granted: 1999-02-09
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Expires: 2016-12-06
Abstract
Abstract An integrated circuit is formed whereby junction of NMOS transistors are formed dissimilar to junctions of PMOS transistors. The NMOS transistors include an LDD area, an MDD area and a heavy concentration source/drain area. Conversely, the PMOS transistor include an LDD area and a source/drain area. The NMOS transistor junction is formed dissimilar from the PMOS transistor junction to take into account the less mobile nature of the junction dopants relative to the PMOS dopants. Thus, a lessening of the LDD area and the inclusion of an MDD area provide lower source/drain resistance and higher ohmic connectivity in the NMOS device. The PMOS junction includes a relatively large LDD area so as to draw the highly mobile, heavy concentration boron atoms away from the PMOS channel.
Inventors
- 👤 H. Jim Fulford, Jr.
- 👤 Mark I. Gardner
- 👤 Derick J. Wristers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:08
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/601; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
273 words
A CMOS integrated circuit, comprising: a first gate dielectric and a second gate dielectric arranged a lateral spaced distance apart across a semiconductor substrate; a first gate conductor extending across the first gate dielectric between a first opposed pair of sidewall surfaces; a second gate conductor extending across the second gate dielectric between a second opposed pair of sidewall surfaces; first and second pairs of dielectric spacers configured upon the first and second pairs of sidewall surfaces, respectively; n-type lightly doped drain areas formed within the semiconductor substrate self-aligned to the first pair of sidewall surfaces, wherein the n-type lightly doped drain areas comprise a first concentration of n-type dopant species; n-type medium doped drain areas formed within the semiconductor substrate spaced from the first pair of sidewall surfaces by a first spaced distance, wherein the n-type medium doped drain areas comprise a second concentration of n-type dopant species; n-type source and drain areas formed within the semiconductor substrate spaced from the first sidewall surfaces by a second spaced distance which is greater than the first spaced distance, wherein the n-type source and drain areas comprise a third concentration of n-type dopant species; p-type lightly doped drain areas formed within the semiconductor substrate self-aligned to the second pair of sidewall surfaces, wherein the p-type lightly doped drain areas comprise a fourth concentration of p-type dopant species; and p-type source and drain areas formed within the semiconductor substrate spaced from the second pair of sidewall surfaces by a third distance which is substantially equivalent to the second spaced distance, wherein the p-type source and drain areas comprise a fifth concentration of p-type dopant species.
Claim 2
Dependent Claim
273 words
A CMOS integrated circuit, comprising: a first gate dielectric and a second gate dielectric arranged a lateral spaced distance apart across a semiconductor substrate; a first gate conductor extending across the first gate dielectric between a first opposed pair of sidewall surfaces; a second gate conductor extending across the second gate dielectric between a second opposed pair of sidewall surfaces; first and second pairs of dielectric spacers configured upon the first and second pairs of sidewall surfaces, respectively; n-type lightly doped drain areas formed within the semiconductor substrate self-aligned to the first pair of sidewall surfaces, wherein the n-type lightly doped drain areas comprise a first concentration of n-type dopant species; n-type medium doped drain areas formed within the semiconductor substrate spaced from the first pair of sidewall surfaces by a first spaced distance, wherein the n-type medium doped drain areas comprise a second concentration of n-type dopant species; n-type source and drain areas formed within the semiconductor substrate spaced from the first sidewall surfaces by a second spaced distance which is greater than the first spaced distance, wherein the n-type source and drain areas comprise a third concentration of n-type dopant species; p-type lightly doped drain areas formed within the semiconductor substrate self-aligned to the second pair of sidewall surfaces, wherein the p-type lightly doped drain areas comprise a fourth concentration of p-type dopant species; and p-type source and drain areas formed within the semiconductor substrate spaced from the second pair of sidewall surfaces by a third distance which is substantially equivalent to the second spaced distance, wherein the p-type source and drain areas comprise a fifth concentration of p-type dopant species.
Claim 3
Dependent Claim
39 words
The integrated circuit as recited in claim 1, wherein said first and second gate conductors comprise polycrystalline silicon patterned between said first and second pairs of sidewall surfaces, said first and second pairs of sidewall surfaces being substantially vertical.
Claim 4
Dependent Claim
22 words
The integrated circuit as recited in claim 1, wherein said first and second pairs of sidewall surfaces comprise thermally grown polysilicon oxide.
Claim 5
Dependent Claim
21 words
The integrated circuit as recited in claim 1, wherein said first and second pairs of dielectric spacers comprise deposited polysilicon oxide.
Claim 6
Dependent Claim
20 words
The integrated circuit as recited in claim 1, wherein said first and second pairs of dielectric spacers comprise silicon nitride.
Claim 7
Dependent Claim
44 words
The integrated circuit as recited in claim 1, wherein said first and second pairs of dielectric spacers comprise polycrystalline silicon configured upon said first and second pairs of sidewall surfaces, respectively, said first and second pairs of sidewall surfaces comprising thermally grown polysilicon oxide.
Claim 8
Dependent Claim
32 words
The integrated circuit as recited in claim 1, further comprising metal silicide configured upon upper surfaces of the first and second gate conductors and the n-type and p-type source and drain areas.
Claim 9
Dependent Claim
63 words
The integrated circuit as recited in claim 1, wherein said second concentration of n-type dopant species is greater than said first concentration of n-type dopant species, and wherein said third concentration of n-type dopant species is greater than said second concentration of dopant species, and wherein said fifth concentration of p-type dopant species is greater than said fourth concentration of p-type dopant species.
Claim 10
Dependent Claim
60 words
The integrated circuit of claim 1, further comprising first and second pairs of conductive spacers spaced from the first and second pairs of sidewall surfaces, respectively, by the first spaced distance, wherein the first and second pairs of dielectric spacers are arranged between the first and second pairs of sidewall surfaces and the first and second pairs of conductive spacers.
Claim 11
Dependent Claim
254 words
An integrated circuit, comprising: a first gate dielectric and a second gate dielectric arranged a lateral spaced distance apart across a semiconductor substrate; a first gate conductor extending across the first gate dielectric between a first opposed pair of sidewall surfaces; a second gate conductor extending across the second gate dielectric between a second opposed pair of sidewall surfaces; n-type lightly doped drain areas formed within the semiconductor substrate self-aligned to the first pair of sidewall surfaces, wherein the n-type lightly doped drain areas comprise a first concentration of n-type dopant species; n-type medium doped drain areas formed within the semiconductor substrate spaced from the first pair of sidewall surfaces by a first spaced distance, wherein the n-type medium doped drain areas comprise a second concentration of n-type dopant species; n-type source and drain areas formed within the semiconductor substrate spaced from the first sidewall surfaces by a second spaced distance which is greater than the first spaced distance, wherein the n-type source and drain areas comprise a third concentration of n-type dopant species; p-type lightly doped drain areas formed within the semiconductor substrate self-aligned to the second pair of sidewall surfaces, wherein the p-type lightly doped drain areas comprise a fourth concentration of p-type dopant species; and p-type source and drain areas formed within the semiconductor substrate spaced from the second pair of sidewall surfaces by a third distance which is substantially equivalent to the second spaced distance, wherein the p-type source and drain areas comprise a fifth concentration of p-type dopant species.
Claim 12
Dependent Claim
254 words
An integrated circuit, comprising: a first gate dielectric and a second gate dielectric arranged a lateral spaced distance apart across a semiconductor substrate; a first gate conductor extending across the first gate dielectric between a first opposed pair of sidewall surfaces; a second gate conductor extending across the second gate dielectric between a second opposed pair of sidewall surfaces; n-type lightly doped drain areas formed within the semiconductor substrate self-aligned to the first pair of sidewall surfaces, wherein the n-type lightly doped drain areas comprise a first concentration of n-type dopant species; n-type medium doped drain areas formed within the semiconductor substrate spaced from the first pair of sidewall surfaces by a first spaced distance, wherein the n-type medium doped drain areas comprise a second concentration of n-type dopant species; n-type source and drain areas formed within the semiconductor substrate spaced from the first sidewall surfaces by a second spaced distance which is greater than the first spaced distance, wherein the n-type source and drain areas comprise a third concentration of n-type dopant species; p-type lightly doped drain areas formed within the semiconductor substrate self-aligned to the second pair of sidewall surfaces, wherein the p-type lightly doped drain areas comprise a fourth concentration of p-type dopant species; and p-type source and drain areas formed within the semiconductor substrate spaced from the second pair of sidewall surfaces by a third distance which is substantially equivalent to the second spaced distance, wherein the p-type source and drain areas comprise a fifth concentration of p-type dopant species.
Claim 13
Dependent Claim
39 words
The integrated circuit as recited in claim 10, wherein said first and second gate conductors comprise polycrystalline silicon patterned between said first and second pairs of sidewall surfaces, said first and second pairs of sidewall surfaces being substantially vertical.
Claim 14
Dependent Claim
21 words
The integrated circuit as recited in claim 10, wherein said first and second pairs of sidewall surfaces comprise thermally grown oxide.
Claim 15
Dependent Claim
63 words
The integrated circuit as recited in claim 10, wherein said second concentration of n-type dopant species is greater than said first concentration of n-type dopant species, and wherein said third concentration of n-type dopant species is greater than said second concentration of dopant species, and wherein said fifth concentration of p-type dopant species is greater than said fourth concentration of p-type dopant species.
Claim 16
Dependent Claim
32 words
The integrated circuit as recited in claim 10, further comprising metal silicide formed upon upper surfaces of the first and second gate conductors and the n-type and p-type source and drain areas.
References Cited (Backward Citations)
US4172260A
Cited
US4949136A
Cited
JPH02280342A
Cited
US5015598A
Cited
US5444282A
Cited
JPH04208571A
Cited
US5091763A
Cited
US5422506A
Cited
US5241203A
Cited
JPH05267327A
Cited
US5498555A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-02-08 | 2002-08-10 | 2003-02-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-08 | 2006-08-10 | 2007-02-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-08 | 2010-08-10 | 2011-02-09 | $7700.00 | Window Closed / Lapsed |