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Patent US5869866A successfully refreshed from Google Patents.
US5869866A
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Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions
Assignee: Advanced Micro Devices Inc
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Filing: 1996-12-06
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Granted: 1999-02-09
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Expires: 2016-12-06
Abstract
Abstract An integrated circuit is formed whereby junctions of NMOS transistors are formed dissimilar to junctions of PMOS transistors. The NMOS transistors include an LDD area, at least one MDD area, and a heavy concentration source/drain area. Conversely, the PMOS transistor includes an LDD area and a source/drain area. The NMOS transistor junction is formed dissimilar from the PMOS transistor junction to take into account, inter alia, the less mobile nature of the junction dopants relative to the PMOS dopants. Thus, a lessening of the LDD area and the inclusion of an MDD area provides lower source-drain resistance and higher ohmic connectivity in the NMOS device. The PMOS junction includes a relatively large LDD area so as to draw the highly mobile, heavy concentration boron atoms away from the PMOS channel.
Inventors
- 👤 H. Jim Fulford, Jr.
- 👤 Mark I. Gardner
- 👤 Derick J. Wristers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:28
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10D30/00; H10D30/60; H10D30/601; H10D64/00; H10D64/01; H10D64/015; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/0184; H10D84/02; H10D84/03; H10D84/038; H10D84/8312; H10D84/8316
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
168 words
An integrated circuit, comprising: a gate dielectric arranged across a semiconductor substrate; a gate conductor extending across the gate dielectric between an opposing pair of sidewall surfaces; a spacer extending laterally from each of the sidewall surfaces to form a spacer sidewall surface spaced from the gate conductor; a first MDD area implanted in the semiconductor substrate, the first MDD area comprising a first depth, wherein the first MDD area is aligned with the spacer sidewall surface; a second MDD area implanted in the semiconductor substrate, the second MDD area comprising a second depth, wherein the second MDD area is positioned a first distance from the spacer, and wherein the second depth is deeper than the first depth; and a source/drain region implanted in the semiconductor substrate, the source/drain region comprising a third depth, wherein the source/drain region is positioned a second distance from the spacer, and wherein the second distance is greater than the first distance, and wherein the third depth is greater than the second depth.
Claim 2
Dependent Claim
168 words
An integrated circuit, comprising: a gate dielectric arranged across a semiconductor substrate; a gate conductor extending across the gate dielectric between an opposing pair of sidewall surfaces; a spacer extending laterally from each of the sidewall surfaces to form a spacer sidewall surface spaced from the gate conductor; a first MDD area implanted in the semiconductor substrate, the first MDD area comprising a first depth, wherein the first MDD area is aligned with the spacer sidewall surface; a second MDD area implanted in the semiconductor substrate, the second MDD area comprising a second depth, wherein the second MDD area is positioned a first distance from the spacer, and wherein the second depth is deeper than the first depth; and a source/drain region implanted in the semiconductor substrate, the source/drain region comprising a third depth, wherein the source/drain region is positioned a second distance from the spacer, and wherein the second distance is greater than the first distance, and wherein the third depth is greater than the second depth.
Claim 3
Dependent Claim
22 words
The integrated circuit as recited in claim 1, wherein said gate conductor comprises polycrystalline silicon oriented between substantially vertical said sidewall surfaces.
Claim 4
Dependent Claim
16 words
The integrated circuit as recited in claim 1, wherein said sidewall surfaces comprise thermally grown oxide.
Claim 5
Dependent Claim
13 words
The integrated circuit as recited in claim 1, wherein said spacer comprises nitride.
Claim 6
Dependent Claim
27 words
The integrated circuit as recited in claim 1, wherein the sidewall surfaces comprise thermally grown oxide, and wherein said spacer comprises nitride configured upon said sidewall surfaces.
Claim 7
Dependent Claim
196 words
An integrated circuit, comprising: a semiconductor topography; a gate dielectric arranged across a semiconductor substrate; a gate conductor extending across the semiconductor topography; and an LDD area implanted in the semiconductor substrate, the LDD area comprising a first depth, wherein the LDD area is aligned with an edge of the gate conductor; a first MDD area implanted in the semiconductor substrate, the first MDD area comprising a second depth, wherein the MDD area is positioned a first distance from the gate conductor, and wherein the second depth is deeper than the first depth; a second MDD area implanted in the semiconductor substrate, the second MDD area comprising a third depth, wherein the second MDD area is positioned a second distance from the gate conductor, and wherein the second distance is greater than the first distance, and wherein the third depth is greater than the second depth; a source/drain region implanted in the semiconductor substrate, the source/drain region comprising a fourth depth, wherein the source/drain region is positioned a third distance from the gate conductor, and wherein the third distance is greater than the second distance, and wherein the fourth depth is greater than the third depth.
Claim 8
Dependent Claim
196 words
An integrated circuit, comprising: a semiconductor topography; a gate dielectric arranged across a semiconductor substrate; a gate conductor extending across the semiconductor topography; and an LDD area implanted in the semiconductor substrate, the LDD area comprising a first depth, wherein the LDD area is aligned with an edge of the gate conductor; a first MDD area implanted in the semiconductor substrate, the first MDD area comprising a second depth, wherein the MDD area is positioned a first distance from the gate conductor, and wherein the second depth is deeper than the first depth; a second MDD area implanted in the semiconductor substrate, the second MDD area comprising a third depth, wherein the second MDD area is positioned a second distance from the gate conductor, and wherein the second distance is greater than the first distance, and wherein the third depth is greater than the second depth; a source/drain region implanted in the semiconductor substrate, the source/drain region comprising a fourth depth, wherein the source/drain region is positioned a third distance from the gate conductor, and wherein the third distance is greater than the second distance, and wherein the fourth depth is greater than the third depth.
References Cited (Backward Citations)
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