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US5869351A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of producing an electro-optical device

Assignee: EIDOS DISPLAY LLC
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Filing: 1996-11-07
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Granted: 1999-02-09
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Expires: 2016-11-07
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Abstract

Abstract A method for producing an electro-optical device comprising a first photolithographic step of forming a transparent pixel electrode, a second photolithographic of forming a gate electrode and a gate wiring, a third photolithographic step of forming a contact holes in an insulator film leading to the pixel electrode and the gate wiring, a fourth photolithographic step of forming a source electrode and a drain electrode and a channel portion above the gate electrode, and a fifth photolithographic step of forming a contact hole in a passivation film and isolating the semi-conductor active film below the source electrode, the drain electrode and the source wiring from other adjacent portions. The number of photolithographic steps can be reduced, to improve the yield and decrease the production cost adjacent thin film transistors.

Inventors

  • 👤 Ken Kawahata
  • 👤 Akira Nakano
  • 👤 Hirofumi Fukui
  • 👤 Hiroyuki Hebiguchi
  • 👤 Kenji Yamamoto
  • 👤 Chisato Iwasaki

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 10:07
CPC Classifications
G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; H; H10; H10D; H10D86/00; H10D86/01; H10D86/021; H10D86/0231; H10D86/40; H10D86/60

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 367 words
A method for producing an electro-optical device in which an electro-optical material is put between a pair of substrates opposed to each other, at least a portion of opposing surfaces of the substrates is insulative, a plurality of source wirings and a plurality of gate wirings are formed crossing each other on the surface of one of the substrates and a transparent pixel electrode and a thin film transistor are formed at each of crossing points between the source wirings and the gate wirings, wherein the method comprises: a step C1 of forming a first metal film on the surface of the one substrate, a first photolithographic step C2 of patterning the first metal film to form a gate electrode and a gate wiring, a step C3 of forming a first insulator film, a semiconductor active film, an ohmic contact film and a metal film on the surface of the one substrate after the first photolithographic step, a second photolithographic step C4 of patterning the semiconductor active film, the ohmic contact and the metal film to form a patterned trilayer film portion above the gate electrode in a state isolated from other portions, a third photolithographic step C5 of patterning the first insulator film to form a contact hole reaching the gate wiring, a step C6 of forming a transparent conductive film for a transparent pixel electrode, a source electrode and a drain electrode on the surface of the substrate after the third photolithographic step, a fourth photolithographic step C7 of patterning the transparent conductive film to form a source electrode, a source wiring, a drain electrode and a transparent pixel electrode, and patterning the transparent conductive film, the metal layer and the ohmic contact film above the gate electrode to form a channel portion above the gate electrode, a step C8 of forming a passivation film on the surface of the one substrate after the fourth photolithographic step, and a fifth photolithographic step C9 of patterning the passivation film to remove a portion of the passivation film above the transparent pixel electrode and make a portion above the transparent pixel electrode light permeable and forming a contact hole for source wiring and gate wiring connection terminals.
Claim 2
Independent Claim 367 words
A method for producing an electro-optical device in which an electro-optical material is put between a pair of substrates opposed to each other, at least a portion of opposing surfaces of the substrates is insulative, a plurality of source wirings and a plurality of gate wirings are formed crossing each other on the surface of one of the substrates and a transparent pixel electrode and a thin film transistor are formed at each of crossing points between the source wirings and the gate wirings, wherein the method comprises: a step C1 of forming a first metal film on the surface of the one substrate, a first photolithographic step C2 of patterning the first metal film to form a gate electrode and a gate wiring, a step C3 of forming a first insulator film, a semiconductor active film, an ohmic contact film and a metal film on the surface of the one substrate after the first photolithographic step, a second photolithographic step C4 of patterning the semiconductor active film, the ohmic contact and the metal film to form a patterned trilayer film portion above the gate electrode in a state isolated from other portions, a third photolithographic step C5 of patterning the first insulator film to form a contact hole reaching the gate wiring, a step C6 of forming a transparent conductive film for a transparent pixel electrode, a source electrode and a drain electrode on the surface of the substrate after the third photolithographic step, a fourth photolithographic step C7 of patterning the transparent conductive film to form a source electrode, a source wiring, a drain electrode and a transparent pixel electrode, and patterning the transparent conductive film, the metal layer and the ohmic contact film above the gate electrode to form a channel portion above the gate electrode, a step C8 of forming a passivation film on the surface of the one substrate after the fourth photolithographic step, and a fifth photolithographic step C9 of patterning the passivation film to remove a portion of the passivation film above the transparent pixel electrode and make a portion above the transparent pixel electrode light permeable and forming a contact hole for source wiring and gate wiring connection terminals.

References Cited (Backward Citations)

US4624737A Cited
US5210045A Cited
US5585290A Cited
US5496752A Cited
US5346833A Cited
US5466618A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-02-08 2002-08-10 2003-02-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-02-08 2006-08-10 2007-02-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-02-08 2010-08-10 2011-02-09 $7700.00 Window Closed / Lapsed

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