Patent US5866460A successfully refreshed from Google Patents.
US5866460A
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Method of forming a multiple inplant lightly doped drain (MILDD) field effect transistor
Assignee: Micron Technology Inc
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Filing: 1997-04-10
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Granted: 1999-02-02
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Expires: 2017-04-10
Abstract
Abstract A multiple implant lightly doped drain ("MILDD") field effect transistor is disclosed. The transistor includes a channel, a gate, a dielectric structure that separates the gate from the channel, a source region and a drain region. The drain region has a first drain subregion, a second drain subregion and a third drain subregion. Each drain subregion has a dopant concentration that differs from that of the other two drain subregions. A method of forming the same is also disclosed.
Inventors
- 👤 Salman Akram
- 👤 Akram Ditali
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:51
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/0221; H10D30/60; H10D30/601; H10D30/603; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D64/00; H10D64/01; H10D64/021; Y; Y10; Y10S; Y10S257/00; Y10S257/90; Y10S257/929
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
183 words
A method of forming a transistor on a substrate, comprising the following steps: forming a dielectric layer overlying the substrate; forming a gate structure overlying the dielectric layer, the gate structure having a first sidewall and a second sidewall, whereby a first contact region, a channel region and a second contact region are defined within the substrate; forming first, second and third subregions within the second contact region, each subregion having a dopant concentration that differs from that of the other two subregions, wherein the step of forming the subregions comprises the following steps: forming a single layer sidewall spacer overlying the second sidewall; introducing a first dopant into the substrate to form the first subregion, the first subregion being generally aligned with the sidewall spacer; reducing the thickness of the sidewall spacer; introducing a second dopant into the substrate to form the second subregion, the second subregion being generally aligned with the thickness-reduced sidewall spacer; substantially removing the sidewall spacer; introducing a third dopant into the substrate to form the third subregion, the third subregion being generally aligned with the second sidewall.
Claim 2
Independent Claim
183 words
A method of forming a transistor on a substrate, comprising the following steps: forming a dielectric layer overlying the substrate; forming a gate structure overlying the dielectric layer, the gate structure having a first sidewall and a second sidewall, whereby a first contact region, a channel region and a second contact region are defined within the substrate; forming first, second and third subregions within the second contact region, each subregion having a dopant concentration that differs from that of the other two subregions, wherein the step of forming the subregions comprises the following steps: forming a single layer sidewall spacer overlying the second sidewall; introducing a first dopant into the substrate to form the first subregion, the first subregion being generally aligned with the sidewall spacer; reducing the thickness of the sidewall spacer; introducing a second dopant into the substrate to form the second subregion, the second subregion being generally aligned with the thickness-reduced sidewall spacer; substantially removing the sidewall spacer; introducing a third dopant into the substrate to form the third subregion, the third subregion being generally aligned with the second sidewall.
Claim 3
Dependent Claim
37 words
The method of claim 1, further comprising the step of forming a fourth subregion within the second contact region, the fourth subregion having a dopant concentration that differs from that of the first, second and third subregions.
Claim 4
Dependent Claim
22 words
The method of claim 1, wherein the dopant introduction steps are performed at energy levels of from approximately 20 to 130 keV.
Claim 5
Dependent Claim
22 words
The method of claim 1, wherein the dopant introduction steps are performed at energy levels of from approximately 30 to 100 keV.
Claim 6
Dependent Claim
37 words
The method of claim 1, wherein the step of forming the sidewall spacer comprises the following steps: forming a second dielectric layer overlying the dielectric layer and the gate structure; and anisotropically etching the second dielectric layer.
Claim 7
Dependent Claim
36 words
The method of claim 1, further comprising the step of forming first, second and third subregions within the first contact region, each subregion having a dopant concentration that differs from that of the other two subregions.
Claim 8
Dependent Claim
19 words
The method of claim 1, further comprising the step of forming an anti-punchthrough region underlying the second contact region.
Claim 9
Independent Claim
188 words
A method of forming a transistor on a substrate, comprising the following steps: forming a dielectric layer overlying the substrate; forming a gate structure overlying the dielectric layer, the gate structure having a first sidewall and a second sidewall, whereby a first contact region, a channel region and a second contact region are defined within the substrate; forming first, second and third subregions within the second contact region, each subregion having a dopant concentration that differs from that of the other two subregions, wherein the step of forming the subregions comprises the following steps: forming a single layer sidewall spacer overlying the second sidewall; introducing a first dopant into the substrate to form the first subregion, the first subregion being generally aligned with the sidewall spacer; reducing the thickness of the sidewall spacer; introducing a second dopant into the substrate to form the second subregion, the second subregion being generally aligned with the thickness-reduced sidewall spacer; further reducing the thickness of the sidewall spacer; introducing a third dopant into the substrate to form the third subregion, the third subregion being generally aligned with the further thickness-reduced sidewall spacer.
Claim 10
Independent Claim
188 words
A method of forming a transistor on a substrate, comprising the following steps: forming a dielectric layer overlying the substrate; forming a gate structure overlying the dielectric layer, the gate structure having a first sidewall and a second sidewall, whereby a first contact region, a channel region and a second contact region are defined within the substrate; forming first, second and third subregions within the second contact region, each subregion having a dopant concentration that differs from that of the other two subregions, wherein the step of forming the subregions comprises the following steps: forming a single layer sidewall spacer overlying the second sidewall; introducing a first dopant into the substrate to form the first subregion, the first subregion being generally aligned with the sidewall spacer; reducing the thickness of the sidewall spacer; introducing a second dopant into the substrate to form the second subregion, the second subregion being generally aligned with the thickness-reduced sidewall spacer; further reducing the thickness of the sidewall spacer; introducing a third dopant into the substrate to form the third subregion, the third subregion being generally aligned with the further thickness-reduced sidewall spacer.
Claim 11
Independent Claim
178 words
A method of forming a transistor on a substrate, comprising the following steps: forming a dielectric layer overlying the substrate; forming a gate structure overlying the dielectric layer, the gate structure having a first sidewall and a second sidewall, whereby a first contact region, a channel region and a second contact region are defined within the substrate; forming first, second and third subregions within the second contact region, each subregion having a dopant concentration that differs from that of the other two subregions, wherein the step of forming the subregions comprises the following steps: introducing a first dopant into the substrate to form the first subregion, the first subregion being generally aligned with the second sidewall; forming a single layer sidewall spacer overlying the second sidewall; introducing a second dopant into the substrate to form the second subregion, the second subregion being generally aligned with the sidewall spacer; reducing the thickness of the sidewall spacer; introducing a third dopant into the substrate to form the third subregion, the third subregion being generally aligned with the thickness-reduced sidewall spacer.
Claim 12
Independent Claim
178 words
A method of forming a transistor on a substrate, comprising the following steps: forming a dielectric layer overlying the substrate; forming a gate structure overlying the dielectric layer, the gate structure having a first sidewall and a second sidewall, whereby a first contact region, a channel region and a second contact region are defined within the substrate; forming first, second and third subregions within the second contact region, each subregion having a dopant concentration that differs from that of the other two subregions, wherein the step of forming the subregions comprises the following steps: introducing a first dopant into the substrate to form the first subregion, the first subregion being generally aligned with the second sidewall; forming a single layer sidewall spacer overlying the second sidewall; introducing a second dopant into the substrate to form the second subregion, the second subregion being generally aligned with the sidewall spacer; reducing the thickness of the sidewall spacer; introducing a third dopant into the substrate to form the third subregion, the third subregion being generally aligned with the thickness-reduced sidewall spacer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-01 | 2002-08-03 | 2003-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-01 | 2006-08-03 | 2007-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-01 | 2010-08-03 | 2011-02-02 | $7700.00 | Window Closed / Lapsed |