US5862366A — System and method for simulating a multiprocessor…

Claim 1

Independent Claim 116 words

A multiprocessing system comprising: a plurality of processors which includes a test processor and a destination processor other than said test processor; a plurality of I/O devices; and a central interrupt control unit functionally intercoupling said plurality of processors and said plurality of I/O devices, wherein said central interrupt control unit is configured to receive interrupt signals from said plurality of I/O devices and is configured to distribute said interrupt signals to said plurality of processors; and wherein the test processor is configured to operate in a test mode, wherein in said test mode said test processor intercepts interrupt signals targeted to the destination processor and responds to said interrupt signals with corresponding interrupt acknowledge signals.

Claim 2

Dependent Claim 116 words

A multiprocessing system comprising: a plurality of processors which includes a test processor and a destination processor other than said test processor; a plurality of I/O devices; and a central interrupt control unit functionally intercoupling said plurality of processors and said plurality of I/O devices, wherein said central interrupt control unit is configured to receive interrupt signals from said plurality of I/O devices and is configured to distribute said interrupt signals to said plurality of processors; and wherein the test processor is configured to operate in a test mode, wherein in said test mode said test processor intercepts interrupt signals targeted to the destination processor and responds to said interrupt signals with corresponding interrupt acknowledge signals.

Claim 3

Dependent Claim 26 words

The multiprocessing system of claim 1, wherein in said test mode said test processor is configured to emulate operation of others of said plurality of processors.

Claim 4

Dependent Claim 55 words

The multiprocessing system of claim 1, wherein said test processor is configured to verify correct operation of said central interrupt control unit, wherein said central interrupt control unit includes a test register configured to store destination processor identifications, and wherein said test processor determines whether the destination processor identifications correspond to the intercepted interrupt signals.

Claim 5

Dependent Claim 29 words

The multiprocessing system of claim 1, wherein said test processor is configured to initiate delivery of interrupt signals to said central interrupt control unit while in said test mode.

Claim 6

Independent Claim 46 words

A method for testing a multiprocessing interrupt controller, comprising: providing one of a plurality of processors as a master test processor; using said master test processor to initiate and control testing of the multiprocessing interrupt controller; and simulating a multiprocessing environment using said master test processor.

Claim 7

Independent Claim 46 words

A method for testing a multiprocessing interrupt controller, comprising: providing one of a plurality of processors as a master test processor; using said master test processor to initiate and control testing of the multiprocessing interrupt controller; and simulating a multiprocessing environment using said master test processor.

Claim 8

Dependent Claim 39 words

The method for testing a multiprocessing interrupt controller as recited in claim 5, wherein said simulation step further includes said master test processor intercepting interrupt signals directed from said multiprocessing interrupt controller to others of said plurality of processors.

Claim 9

Dependent Claim 43 words

The method for testing a multiprocessing interrupt controller as recited in claim 6, wherein said simulating step further includes said master test processor responding to intercepted interrupt signals with the appropriate interrupt acknowledge signals in lieu of others of said plurality of processors.

Claim 10

Dependent Claim 30 words

The method of testing a multiprocessing interrupt controller as recited in claim 7, further including the step of using said master test processor to verify the results of said testing.

Claim 11

Dependent Claim 38 words

The method of testing a multiprocessing interrupt controller as recited in claim 8, wherein said verifying step further includes identifying whether an intercepted interrupt has been directed to the appropriate one of others of said plurality of processors.

Claim 12

Dependent Claim 37 words

The method of testing a multiprocessing interrupt controller as recited in claim 9, wherein said verifying step further includes determining whether said multiprocessing interrupt controller returns an appropriate interrupt vector in response to said interrupt acknowledge signal.

Claim 13

Dependent Claim 104 words

A computer system, comprising: a central interrupt control unit configured to process a plurality of interrupt signals; a plurality of I/O devices coupled to said central interrupt control unit and configured to assert said plurality of interrupt signals at said central interrupt control unit; and a processor coupled to said central interrupt control unit and configured to receive said plurality of interrupt signals from said central interrupt control unit, wherein said processor is configured to initiate a test mode for testing said central interrupt control unit, wherein in said test mode said processor is configured to emulate the operation of a plurality of processors.

Claim 14

Dependent Claim 104 words

A computer system, comprising: a central interrupt control unit configured to process a plurality of interrupt signals; a plurality of I/O devices coupled to said central interrupt control unit and configured to assert said plurality of interrupt signals at said central interrupt control unit; and a processor coupled to said central interrupt control unit and configured to receive said plurality of interrupt signals from said central interrupt control unit, wherein said processor is configured to initiate a test mode for testing said central interrupt control unit, wherein in said test mode said processor is configured to emulate the operation of a plurality of processors.

Claim 15

Dependent Claim 25 words

The computer system of claim 11, wherein said processor is configured to receive interrupt signals directed by said central interrupt control unit to another processor.

Claim 16

Dependent Claim 43 words

The computer system of claim 11, wherein said central interrupt controller includes a register specifying which processor a directed interrupt is directed to, and wherein said processor is configured to read said register to verify correct operation of said central interrupt control unit.

Claim 17

Dependent Claim 28 words

The computer system of claim 11, wherein said processor is configured to initiate delivery of interrupt signals to said central interrupt control unit while in said test mode.

Claim 18

Dependent Claim 128 words

A testing system comprising: a test processor; a central interrupt control unit including (a) a plurality of interrupt input channels for receiving interrupt stimulus signals, and (b) a plurality of processor interrupt channels for asserting processor interrupt signals to a corresponding plurality of processors including said test processor, wherein said central interrupt control unit controls the assertion of said processor interrupt signals based on said interrupt stimulus signals; wherein said test processor is coupled to each of said processor interrupt channels; wherein said test processor is configured (a) to initiate said stimulus signals to said interrupt input channels, (b) to receive said processor interrupt signals from said plurality of processor interrupt channels, and (c) to determine if said central interrupt control unit processed said interrupt stimulus signals correctly.

Claim 19

Dependent Claim 128 words

A testing system comprising: a test processor; a central interrupt control unit including (a) a plurality of interrupt input channels for receiving interrupt stimulus signals, and (b) a plurality of processor interrupt channels for asserting processor interrupt signals to a corresponding plurality of processors including said test processor, wherein said central interrupt control unit controls the assertion of said processor interrupt signals based on said interrupt stimulus signals; wherein said test processor is coupled to each of said processor interrupt channels; wherein said test processor is configured (a) to initiate said stimulus signals to said interrupt input channels, (b) to receive said processor interrupt signals from said plurality of processor interrupt channels, and (c) to determine if said central interrupt control unit processed said interrupt stimulus signals correctly.

Claim 20

Dependent Claim 28 words

The testing system of claim 15, wherein said interrupt input channels are coupled to receive interrupt stimulus signals from a plurality of I/O devices during an operational mode.

Claim 21

Dependent Claim 44 words

The testing system of claim 15, wherein said test processor is configured to assert acknowledge signals to said central interrupt control unit in response to receiving said processor interrupt signals, wherein each of said acknowledge signals corresponds to one of said processor interrupt signals.

Claim 22

Dependent Claim 56 words

The testing system of claim 17, wherein said test processor is configured to receive interrupt vectors from said central interrupt control unit corresponding to said processor interrupt signals in response to said acknowledge signals, wherein said test processor is further configured to determine if said received interrupt vectors are valid for said respective processor interrupt signals.

Claim 23

Dependent Claim 38 words

The testing system of claim 15, wherein said central interrupt control unit includes a test control register, wherein said test processor initiates said interrupt stimulus signals to said interrupt input channels by writing to said test control register.

Claim 24

Dependent Claim 73 words

The testing system of claim 15, wherein said central interrupt control unit includes a plurality of test status registers, wherein said test status registers record the processing of said interrupt stimulus signals from said interrupt input channels to said processor interrupt channels, wherein said test processor is configured to read said plurality of test status registers after receiving said processor interrupt signals, and to determine if said interrupt stimulus signals were processed correctly.

Claim 25

Dependent Claim 81 words

The testing system of claim 20, wherein said test processor (a) initiates a first interrupt stimulus signal to a first interrupt input channel, (b) receives a first processor interrupt signal from a first processor interrupt channel asserted in response to said first interrupt stimulus signal, (c) reads said test status registers in response to receiving said first processor interrupt signal, and (d) determines if said first interrupt stimulus signal has been processed correctly based on data from said test status registers.

Claim 26

Dependent Claim 46 words

The testing system of claim 21, wherein said test processor is configured to compare said data received from said test status registers to expected results for said test status registers to determine if said first interrupt input channel has correctly processed said first interrupt stimulus signal.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2002-01-18	2002-07-20	2003-01-19	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2006-01-18	2006-07-20	2007-01-19	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2010-01-18	2010-07-20	2011-01-19	$7700.00	Window Closed / Lapsed

System and method for simulating a multiprocessor environment for testing a multiprocessing interrupt controller

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