Patent US5859990A successfully refreshed from Google Patents.
US5859990A
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System for transferring data segments from a first storage device to a second storage device using an alignment stage including even and odd temporary devices
Assignee: Intel Corp
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Filing: 1995-12-29
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Granted: 1999-01-12
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Expires: 2015-12-29
Abstract
Abstract The present invention provides an alignment logic circuit transferring segments of data from a first storage device to a second storage device. The segments of data are aligned in the first storage device, in a first and second dimension, according to a first configuration. The segments of data are aligned in the second storage device, in the first and second dimension according to a second configuration. The alignment logic circuit includes a first alignment stage, a second alignment stage, and an alignment control logic controls the first alignment stage such that the first alignment stage outputs data aligned in the first dimension according to the second configuration, and the second alignment stage outputs data aligned in the second dimension according to the second configuration. It is also provided a computer system with a DMA controller with a Memory Write and Invalidate logic circuit. The Memory Write and Invalidate logic circuit generates a Memory Write and Invalidate enable signal when the DMA byte count is greater than a recall with a cacheline size, and the current transfer adders is a multiple of the cacheline size. The present invention also provides a computer system including a host processor, a first bus coupled to the host processor, a second bus, slave circuit coupled to the second bus, and a direct memory access controller (DMA). The DMA performs DMA transactions between the first and second buses. The DMA controller includes a DMA error handling logic, coupled to the host processor, for receiving a retry signal indicative of a retry request of the slave circuit. The DMA error handling logic also receives an error signal indicative of an error on the first bus. The error handling logic aborts a DMA transfer when the error signal is asserted and the retry signal is deasserted.
Inventors
- 👤 Mark A. Yarch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:08
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
185 words
An apparatus to transfer segments of data from a first storage device to a second storage device, said apparatus comprising: first alignment stage coupled to said first storage device; said segments of data aligned in said first storage device in first and second dimensions according to first configuration, and in said second storage device in said first and second dimensions according to a second configuration; second alignment stage, coupled at an input thereof to said first alignment stage and at an output thereof to said second storage device, said second alignment stage including even and odd temporary devices; alignment control logic to generate first control signal to said first alignment stage to supply to said second alignment stage said segments of data aligned in said first dimension according to said second configuration and to generate second and third control signals to said even and odd temporary storage devices respectively to align said segments in said second dimension according to said second configuration and to provide said segments of data from said even and odd temporary storage devices to said second storage device in consecutive cycles.
Claim 2
Independent Claim
185 words
An apparatus to transfer segments of data from a first storage device to a second storage device, said apparatus comprising: first alignment stage coupled to said first storage device; said segments of data aligned in said first storage device in first and second dimensions according to first configuration, and in said second storage device in said first and second dimensions according to a second configuration; second alignment stage, coupled at an input thereof to said first alignment stage and at an output thereof to said second storage device, said second alignment stage including even and odd temporary devices; alignment control logic to generate first control signal to said first alignment stage to supply to said second alignment stage said segments of data aligned in said first dimension according to said second configuration and to generate second and third control signals to said even and odd temporary storage devices respectively to align said segments in said second dimension according to said second configuration and to provide said segments of data from said even and odd temporary storage devices to said second storage device in consecutive cycles.
Claim 3
Dependent Claim
38 words
The alignment logic circuit of claim 1 wherein said first and second storage devices are partitioned into rows and columns, each intersection of a row and a column defining a storage location for storing one segment of data.
Claim 4
Dependent Claim
31 words
The alignment logic circuit of claim 2 wherein said first dimension corresponds to a column of said storage devices and said second dimension corresponds to a row of said storage devices.
Claim 5
Dependent Claim
42 words
The alignment logic circuit of claim 3 wherein said first configuration has a source address which corresponds to a source row and a source column, said second configuration having a destination address which corresponds to a destination row and a destination column.
Claim 6
Dependent Claim
35 words
The alignment logic circuit of claim 4 wherein said segments of data comprise bytes, each row of said storage devices including a predetermined number N of bytes B(i) for i equal to 0 through N-1.
Claim 7
Dependent Claim
47 words
The alignment logic circuit of claim 5 further including a first bus coupled to said storage device, wherein said bus includes N 8-bit lines L(i) for i equal 0 through N-1, each of said lines L(i) corresponding to one byte B(i) for i equal 0 through N-1.
Claim 8
Dependent Claim
58 words
The alignment logic circuit of claim 6 wherein said first alignment stage includes N first multiplexing devices M1(i) for i equal 0 through N-1, each of said multiplexing devices M1(i) having an input, coupled to one of said lines L(i) for i equal 0 through N-1, an output, and a control gate coupled to said alignment control logic.
Claim 9
Dependent Claim
81 words
The alignment logic circuit of claim 7 wherein said second alignment stage includes N odd temporary storage devices S1(i) and N even temporary storage devices S2(i) for i equal 0 through N-1, each of said S1(i) and S2(i) having an input coupled to said output of said multiplexing devices M(i) for i equal o through N-1, each of said temporary storage devices having an output, each of said temporary storage devices having a control gate coupled to said alignment control logic.
Claim 10
Dependent Claim
70 words
The alignment logic circuit of claim 7 wherein said second alignment stage further includes N second multiplexing devices M2(i) for i equal 0 to N-1, each of said second multiplexing devices M2(i) having a first input coupled to said odd temporary storage devices S1(i) and a second input coupled to said even temporary storage devices S2(i) for i equal 0 through N-1, said second multiplexing devices having a control input.
Claim 11
Independent Claim
107 words
A method for transferring segments of data between first and second storage devices, said segments of data aligned in said first storage device in first and second dimensions according to a first configuration and in said second storage device according to a second configuration, the method comprising: aligning segments of data in a first dimension according to a second configuration; aligning said segments of data, aligned in said first dimension according to said second configuration, in a second dimension in odd and even temporary storage devices; and transferring said segments of data from said odd and even temporary devices to said second storage device in consecutive cycles.
Claim 12
Independent Claim
107 words
A method for transferring segments of data between first and second storage devices, said segments of data aligned in said first storage device in first and second dimensions according to a first configuration and in said second storage device according to a second configuration, the method comprising: aligning segments of data in a first dimension according to a second configuration; aligning said segments of data, aligned in said first dimension according to said second configuration, in a second dimension in odd and even temporary storage devices; and transferring said segments of data from said odd and even temporary devices to said second storage device in consecutive cycles.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-11 | 2002-07-13 | 2003-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-11 | 2006-07-13 | 2007-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-11 | 2010-07-13 | 2011-01-12 | $7700.00 | Window Closed / Lapsed |