Fabrication process of a stack type semiconductor capacitive element

Claim 2

A fabrication process for forming a stack type semiconductor capacitive element, comprising the steps of: selectively forming an insulation layer on the surface of a semiconductor substrate for defining an element region; forming a first amorphous silicon film with an impurity concentration greater than or equal to 1×10 20 (atoms/cm 3 ) on said element region; forming a second amorphous silicon film with an impurity concentration less than or equal to 1×10 18 (atoms/cm 3 ) on said first amorphous silicon film, said second amorphous silicon film and said first amorphous silicon film constituting an amorphous silicon layer for lower electrode; and forming unevenness on the surface of said amorphous silicon layer for lower electrode by a heat treatment.

Claim 3

The fabrication process for forming a semiconductor capacitive element as set forth in claim 1, further comprising the steps of: performing patterning for said amorphous silicon layer for lower electrode after the step of formation of said unevenness to form a lower electrode; forming a capacitance insulation layer on the surface of said lower electrode; and forming an upper electrode over the surface of said capacitance insulation layer.

Claim 4

A fabrication process of a semiconductor capacitive element as set forth in claim 1, wherein said first amorphous silicon film contains phosphorous as an impurity.

Claim 5

A fabrication process of a semiconductor capacitive element as set forth in claim 1, wherein said step of forming said first amorphous silicon film has a step of depositing said first amorphous silicon film by a reaction under atmosphere of gas containing a silane type gas and the impurity; and said step of forming said second amorphous silicon film has a step of depositing said second amorphous silicon film by a reaction under atmosphere of gas containing only said silane type gas.

Claim 6

A fabrication process of a semiconductor capacitive element as set forth in claim 1, wherein said first and second amorphous silicon films are formed at a temperature in a range of 520° to 550° C.

Claim 7

A fabrication process of a semiconductor capacitive element as set forth in claim 1, wherein said step of forming said unevenness has a step of performing heat treatment for said amorphous silicon layer for lower electrode at a temperature in a range of 550° to 580° C.

Claim 8

A fabrication process of a semiconductor capacitive element as set forth in claim 1, wherein said step of forming said unevenness has the steps of: performing heat treatment for said amorphous silicon layer for lower electrode at a temperature in a range of 550° to 580° C. under silane type gas atmosphere; and leaving at the same temperature and the same pressure as that in said heat treatment process.

Claim 9

A fabrication process of a semiconductor capacitive element as set forth in claim 1, wherein said semiconductor substrate is made of an n-type semiconductor layer.

Claim 10

A fabrication process of a semiconductor capacitive element as set forth in claim 1, wherein said semiconductor substrate has an n-type semiconductor region on the surface.

Claim 11

A fabrication process for forming a stack type semiconductor capacitive element, comprising the steps of: selectively forming an insulation layer on the surface of a semiconductor substrate for defining an element region; forming a first amorphous silicon film with an impurity concentration greater than or equal to 1×10 20 (atoms/cm 3 ) on said element region; forming a second amorphous silicon film with an impurity concentration less than or equal to 1×10 18 (atoms/cm 3 ) on said first amorphous silicon film, said second amorphous silicon film and said first amorphous silicon film constituting an amorphous silicon layer for lower electrode; patterning said amorphous silicon layer for lower electrode to form a patterned amorphous silicon layer; forming a side wall of amorphous silicon with an impurity concentration less than or equal to 1×10 18 (atoms/cm 3 ) on the side surface of said patterned amorphous silicon layer; and forming unevenness on the surfaces of said patterned amorphous silicon layer and said side wall by heat treatment and whereby forming a lower electrode having patterned amorphous silicon layer and said side wall with said unevenness.

Claim 12

A fabrication process for forming a stack type semiconductor capacitive element, comprising the steps of: selectively forming an insulation layer on the surface of a semiconductor substrate for defining an element region; forming a first amorphous silicon film with an impurity concentration greater than or equal to 1×10 20 (atoms/cm 3 ) on said element region; forming a second amorphous silicon film with an impurity concentration less than or equal to 1×10 18 (atoms/cm 3 ) on said first amorphous silicon film, said second amorphous silicon film and said first amorphous silicon film constituting an amorphous silicon layer for lower electrode; patterning said amorphous silicon layer for lower electrode to form a patterned amorphous silicon layer; forming a side wall of amorphous silicon with an impurity concentration less than or equal to 1×10 18 (atoms/cm 3 ) on the side surface of said patterned amorphous silicon layer; and forming unevenness on the surfaces of said patterned amorphous silicon layer and said side wall by heat treatment and whereby forming a lower electrode having patterned amorphous silicon layer and said side wall with said unevenness.

Claim 13

A fabrication process of a semiconductor capacitive element as set forth in claim 10, wherein said first amorphous silicon film contains phosphorous as an impurity.

Claim 14

A fabrication process of a semiconductor capacitive element as set forth in claim 10, wherein said step of forming said first amorphous silicon film has a step of depositing said first amorphous silicon film by a reaction under atmosphere of gas containing a silane type gas and the impurity; said step of forming said second amorphous silicon film has a step of depositing said second amorphous silicon film by a reaction under atmosphere of gas containing only said silane type gas; and said step of forming said side wall has a step of forming a third amorphous silicon film on upper surface and side surface of said patterned amorphous silicon layer and a step of performing anisotropic etching for leaving said third amorphous silicon film only on the side surface of said patterned amorphous silicon layer.

Claim 15

A fabrication process of a semiconductor capacitive element as set forth in claim 10, wherein said first to third amorphous silicon films are formed at a forming temperature in a range of 520° to 550° C.

Claim 16

A fabrication process of a semiconductor capacitive element as set forth in claim 10, wherein said step of forming said unevenness has a step of performing heat treatment for said patterned amorphous silicon layer and said side wall at a temperature in a range of 550° to 580° C.

Claim 17

A fabrication process of a semiconductor capacitive element as set forth in claim 10, wherein said step of forming said unevenness comprises the steps of: performing heat treatment for said patterned amorphous silicon layer and said side wall at a temperature in a range of 550° to 580° C. under silane type gas atmosphere; and leaving at the same temperature and the same pressure as that in said heat treatment process.

Claim 18

A fabrication process of a semiconductor capacitive element as set forth in claim 10, wherein said semiconductor substrate is made of an n-type semiconductor layer.

Claim 19

A fabrication process of a semiconductor capacitive element as set forth in claim 10, wherein said semiconductor substrate has an n-type semiconductor region on the surface.

Claim 20

A fabrication process of a semiconductor capacitive element as set forth in claim 10, further comprising the steps of: forming a capacitance insulation layer over the surface of said lower electrode; and forming an upper electrode over the surface of said capacitance insulation layer.

Claim 21

A fabrication process for forming a stack type semiconductor capacitive element, comprising the steps of: forming a lower electrode of said stack type semiconductor capacitive element including the steps of: forming a first doped amorphous silicon film having an impurity concentration greater than or equal to 1×10 20 (atoms/cm 3 ); forming a second doped amorphous silicon film on said first amorphous silicon film, said second doped amorphous silicon film having an impurity concentration less than or equal to 1×10 18 (atoms/cm 3 ); and heating said first doped amorphous silicon film and said second doped amorphous silicon film to form crystal nucleus of a hemispherical grain (HSG) on a surface of said lower electrode.

Claim 22

A fabrication process for forming a stack type semiconductor capacitive element, comprising the steps of: forming a lower electrode of said stack type semiconductor capacitive element including the steps of: forming a first doped amorphous silicon film having an impurity concentration greater than or equal to 1×10 20 (atoms/cm 3 ); forming a second doped amorphous silicon film on said first amorphous silicon film, said second doped amorphous silicon film having an impurity concentration less than or equal to 1×10 18 (atoms/cm 3 ); and heating said first doped amorphous silicon film and said second doped amorphous silicon film to form crystal nucleus of a hemispherical grain (HSG) on a surface of said lower electrode.

Claim 23

The fabrication process as set forth in claim 19, wherein said step of heating to form crystal nucleus of HSG on a surface of said lower electrode is performed at a temperature in a range of about 550° to 580° C.

Claim 24

The fabrication process as set forth in claim 20, wherein said step of heating to form unevenness on a surface of said lower electrode is further performed in a silane type gas atmosphere to form said crystal nucleus of HSG, and further includes the step of growing said crystal nucleus by maintaining a same temperature and a same pressure as performed in said heating step.

Claim 25

The fabrication process as set forth in claim 19, wherein said step of forming a lower electrode further comprises the steps of: patterning said first doped amorphous silicon film and said second doped amorphous silicon film prior to heating to form unevenness on a surface of said lower electrode; and forming a side wall of amorphous silicon having impurity concentration less than or equal to 1×10 18 (atoms/cm 3 ) on the side surface of said patterned first doped amorphous silicon film and said patterned second doped amorphous silicon film.