Method for fabricating capacitive element of semiconductor memory device

Claim 1

A method for fabricating a capacitive element of a semiconductor memory device, the method comprising the steps of: forming a field insulation film in a device isolating surface region of a p-type silicon substrate; forming a gate insulation film in a device building surface region of the p-type silicon substrate; forming a gate electrode as part of a wordline on the gate insulation film; forming a pair of n-type diffusion regions as source and drain regions in the device building surface region of the p-type silicon substrate so that the n-type diffusion regions self-align to the field insulation film and the gate electrode; forming an interlayer insulation film over an entire surface; forming a node-contact hole reaching a corresponding one of the n-type diffusion regions through the interlayer insulation film; providing a first low pressure chemical-vapor deposition using a monosilane (SiH 4 ) gas for forming a non-doped polycrystalline silicon film covering the interlayer insulation film, filling the node-contact hole; introducing an n-type dopant for converting the non-doped polycrystalline silicon film into a first n-type polycrystalline silicon film; providing a second low pressure chemical-vapor deposition using a disilane (Si 2 H 6 ) gas and a phosphine (PH 3 ) gas for forming an n-type doped amorphous silicon film covering the first n-type polycrystalline silicon film; patterning the n-type doped amorphous silicon film and the first n-type polycrystalline silicon film; removing natural oxidation surface scales from the n-type doped amorphous silicon film and the first n-type polycrystalline silicon film; providing a heat treatment under a vacuum pressure for crystallizing the n-type doped amorphous silicon film from a surface thereof, converting the same into a second n-type polycrystalline silicon film with a rugged surface; and forming a capacitive insulation film over the second n-type polycrystalline silicon film to constitute a cell plate electrode.

Claim 2

A method for fabricating a capacitive element of a semiconductor memory device, the method comprising the steps of: forming a field insulation film in a device isolating surface region of a p-type silicon substrate; forming a gate insulation film in a device building surface region of the p-type silicon substrate; forming a gate electrode as part of a wordline on the gate insulation film; forming a pair of n-type diffusion regions as source and drain regions in the device building surface region of the p-type silicon substrate so that the n-type diffusion regions self-align to the field insulation film and the gate electrode; forming an interlayer insulation film over an entire surface; forming a node-contact hole reaching a corresponding one of the n-type diffusion regions through the interlayer insulation film; providing a first low pressure chemical-vapor deposition using a monosilane (SiH 4 ) gas for forming a non-doped polycrystalline silicon film covering the interlayer insulation film, filling the node-contact hole; introducing an n-type dopant for converting the non-doped polycrystalline silicon film into a first n-type polycrystalline silicon film; providing a second low pressure chemical-vapor deposition using a disilane (Si 2 H 6 ) gas and a phosphine (PH 3 ) gas for forming an n-type doped amorphous silicon film covering the first n-type polycrystalline silicon film; patterning the n-type doped amorphous silicon film and the first n-type polycrystalline silicon film; removing natural oxidation surface scales from the n-type doped amorphous silicon film and the first n-type polycrystalline silicon film; providing a heat treatment under a vacuum pressure for crystallizing the n-type doped amorphous silicon film from a surface thereof, converting the same into a second n-type polycrystalline silicon film with a rugged surface; and forming a capacitive insulation film over the second n-type polycrystalline silicon film to constitute a cell plate electrode.

Claim 3

A method for fabricating a capacitive element of a semiconductor memory device, the method comprising the steps of: forming a field insulation film in a device isolating surface region of a p-type silicon substrate; forming a gate insulation film in a device building surface region of the p-type silicon substrate; forming a gate electrode as part of a wordline on the gate insulation film; forming a pair of n-type diffusion regions as source and drain regions in the device building surface region of the p-type silicon substrate so that the n-type diffusion regions self-align to the field insulation film and the gate electrode; forming an interlayer insulation film over an entire surface; forming a node-contact hole reaching a corresponding one of the n-type diffusion regions through the interlayer insulation film; providing a first low pressure chemical-vapor deposition using a monosilane (SiH 4 ) gas and a phosphine (PH 3 ) gas for forming a first n-type doped amorphous silicon film on the interlayer insulation film, covering a side wall and a bottom surface of the node-contact hole; employing a second low pressure chemical-vapor deposition using a monosilane (SiH 4 ) gas for converting the first n-type doped amorphous silicon film into a first n-type polycrystalline silicon film and for forming a non-doped polycrystalline silicon film covering the first n-type polycrystalline silicon film, filling the node-contact hole; introducing an n-type dopant for converting the non-doped polycrystalline silicon film into a second n-type polycrystalline silicon film; providing a third low pressure chemical-vapor deposition using a disilane (Si 2 H 6 ) gas and a phosphine (PH 3 ) gas for forming a second n-type doped amorphous silicon film covering the second n-type polycrystalline silicon film; patterning the second n-type doped amorphous silicon film, the second n-type polycrystalline silicon film and the first n-type polycrystalline silicon film; removing natural oxidation surface scales from the second n-type doped amorphous silicon film, the second n-type polycrystalline silicon film and the first n-type polycrystalline silicon film; providing a heat treatment under a vacuum pressure for crystallizing the second n-type doped amorphous silicon film from a surface thereof, converting the same into a third n-type polycrystalline silicon film with a rugged surface; and providing a capacitive insulation film over the third n-type polycrystalline silicon film to constitute a cell plate electrode.

Claim 4

A method for fabricating a capacitive element of a semiconductor memory device, the method comprising the steps of: forming a field insulation film in a device isolating surface region of a p-type silicon substrate; forming a gate insulation film in a device building surface region of the p-type silicon substrate; forming a gate electrode as part of a wordline on the gate insulation film; forming a pair of n-type diffusion regions as source and drain regions in the device building surface region of the p-type silicon substrate so that the n-type diffusion regions self-align to the field insulation film and the gate electrode; forming an interlayer insulation film over an entire surface; forming a node-contact hole reaching a corresponding one of the n-type diffusion regions through the interlayer insulation film; providing a first low pressure chemical-vapor deposition using a monosilane (SiH 4 ) gas and a phosphine (PH 3 ) gas for forming a first n-type doped amorphous silicon film on the interlayer insulation film, covering a side wall and a bottom surface of the node-contact hole; employing a second low pressure chemical-vapor deposition using a monosilane (SiH 4 ) gas for converting the first n-type doped amorphous silicon film into a first n-type polycrystalline silicon film and for forming a non-doped polycrystalline silicon film covering the first n-type polycrystalline silicon film, filling the node-contact hole; introducing an n-type dopant for converting the non-doped polycrystalline silicon film into a second n-type polycrystalline silicon film; providing a third low pressure chemical-vapor deposition using a disilane (Si 2 H 6 ) gas and a phosphine (PH 3 ) gas for forming a second n-type doped amorphous silicon film covering the second n-type polycrystalline silicon film; patterning the second n-type doped amorphous silicon film, the second n-type polycrystalline silicon film and the first n-type polycrystalline silicon film; removing natural oxidation surface scales from the second n-type doped amorphous silicon film, the second n-type polycrystalline silicon film and the first n-type polycrystalline silicon film; providing a heat treatment under a vacuum pressure for crystallizing the second n-type doped amorphous silicon film from a surface thereof, converting the same into a third n-type polycrystalline silicon film with a rugged surface; and providing a capacitive insulation film over the third n-type polycrystalline silicon film to constitute a cell plate electrode.

Claim 5

A method for fabricating a capacitive element of a semiconductor memory device, the method comprising the steps of: forming a field insulation film in a device isolating surface region of a p-type silicon substrate; forming a gate insulation film in a device building surface region of the p-type silicon substrate; forming a gate electrode as part of a wordline on the gate insulation film; forming a pair of n-type diffusion regions as source and drain regions in the device building surface region of the p-type silicon substrate so that the n-type diffusion regions self-align to the field insulation film and the gate electrode; forming an interlayer insulation film over an entire surface; forming a node-contact hole reaching a corresponding one of the n-type diffusion regions through the interlayer insulation film; providing a first low pressure chemical-vapor deposition using a monosilane (SiH 4 ) gas and a phosphine (PH 3 ) gas for forming a first n-type doped amorphous silicon film on the interlayer insulation film, covering a side wall and a bottom surface of the node-contact hole; providing a second low pressure chemical-vapor deposition using a disilane (Si 2 H 6 ) gas and a phosphine (PH 3 ) gas for forming a second n-type doped amorphous silicon film covering a first n-type polycrystalline silicon film, filling the node-contact hole; patterning the second n-type doped amorphous silicon film and the first n-type polycrystalline silicon film; removing natural oxidation surface scales from the second n-type doped amorphous silicon film and the first n-type doped amorphous silicon film; providing a heat treatment under a vacuum pressure for crystallizing the second n-type doped amorphous silicon film and the first n-type doped amorphous silicon film from surfaces thereof, converting the same into a second n-type polycrystalline silicon film and a first n-type polycrystalline silicon film, respectively, with rugged surfaces; and forming a capacitive insulation film over the second n-type polycrystalline silicon film and the first n-type polycrystalline silicon film to constitute a cell plate electrode.

Claim 6

A method for fabricating a capacitive element of a semiconductor memory device, the method comprising the steps of: forming a field insulation film in a device isolating surface region of a p-type silicon substrate; forming a gate insulation film in a device building surface region of the p-type silicon substrate; forming a gate electrode as part of a wordline on the gate insulation film; forming a pair of n-type diffusion regions as source and drain regions in the device building surface region of the p-type silicon substrate so that the n-type diffusion regions self-align to the field insulation film and the gate electrode; forming an interlayer insulation film over an entire surface; forming a node-contact hole reaching a corresponding one of the n-type diffusion regions through the interlayer insulation film; providing a first low pressure chemical-vapor deposition using a monosilane (SiH 4 ) gas and a phosphine (PH 3 ) gas for forming a first n-type doped amorphous silicon film on the interlayer insulation film, covering a side wall and a bottom surface of the node-contact hole; providing a second low pressure chemical-vapor deposition using a disilane (Si 2 H 6 ) gas and a phosphine (PH 3 ) gas for forming a second n-type doped amorphous silicon film covering a first n-type polycrystalline silicon film, filling the node-contact hole; patterning the second n-type doped amorphous silicon film and the first n-type polycrystalline silicon film; removing natural oxidation surface scales from the second n-type doped amorphous silicon film and the first n-type doped amorphous silicon film; providing a heat treatment under a vacuum pressure for crystallizing the second n-type doped amorphous silicon film and the first n-type doped amorphous silicon film from surfaces thereof, converting the same into a second n-type polycrystalline silicon film and a first n-type polycrystalline silicon film, respectively, with rugged surfaces; and forming a capacitive insulation film over the second n-type polycrystalline silicon film and the first n-type polycrystalline silicon film to constitute a cell plate electrode.