Patent US5858815A successfully refreshed from Google Patents.
US5858815A
Expired / Lapsed
US
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Semiconductor package and method for fabricating the same
Assignee: Amkor Technology Singapore Holding Pte Ltd
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Filing: 1996-12-11
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Granted: 1999-01-12
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Expires: 2016-12-11
Abstract
Abstract A process for manufacturing chip size semiconductor package with a light, thin, and compact structure having a reduced size of its semiconductor chip while having an increased number of pins For the package, it is possible to use either the semiconductor chip having bond pads arranged on end portions of the chip or the semiconductor chip having bond pads arranged on the central portion of the chip. In either case, input/output terminals of the package are arranged in the form of an area array. Accordingly, when the package is mounted on an electronic appliance, its mounting area can be minimized, thereby achieving a compactness of the final product.
Inventors
- 👤 Young Wook Heo
- 👤 Byung Joon Han
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:34
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/01; H10W72/0198; H10W76/00; H10W76/10; H10W76/12; H10W74/00; H10W74/10; H10W74/111; H10W74/129; H10W72/50; H10W72/531; H10W72/5366; H10W72/541; H10W72/5445; H10W72/551; H10W72/552; H10W72/5522; H10W72/851; H10W72/853; H10W72/865; H10W72/874; H10W72/884; H10W72/90; H10W72/931; H10W72/932; H10W90/00; H10W90/701; H10W90/731; H10W90/734; H10W90/736; H10W90/751; H10W90/754; H10W90/756
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
279 words
A method for fabricating a semiconductor package comprising the steps of: providing a wafer forming semiconductor chips each having an integrated electronic circuit and a plurality of bond pads each adapted to send a signal from the electronic circuit to the outside of the package; forming a multi-layer film which has the same size as the wafer, consists of two non-conductive film layers and a conductive layer, and is formed by forming a conductive layer over a first non-conductive film which is a lower one of the two layers, patterning the conductive layer to form the circuit patterns, and laminating a second non-conductive film on the circuit patterns; attaching the multi-layer film to the wafer by adhesive means in such a manner the bond pad regions defined at the semiconductor chips of the wafer are exposed through the opened portions of the multi-layer film; bonding bond fingers provided at the circuit patterns of the multi-layer film to the bond pads of the semiconductor chips by wires, respectively; covering a sealant layer over the opened portions of the multi-layer film, thereby protecting the wires from external oxidation and erosion; baking the sealant layer in an oven or furnace at a temperature of 150° C. or more; seating solder balls on solder ball lands provided at the multi-layer film, respectively, and reflowing the solder balls in the oven or furnace at a temperature of 200° C. or more, thereby bonding the solder balls to the circuit patterns; cutting the wafer along its street lines using a sawing device so that it can be divided into individual semiconductor chips, thereby forming chip size packages having the same size as their semiconductor chips.
Claim 2
Independent Claim
279 words
A method for fabricating a semiconductor package comprising the steps of: providing a wafer forming semiconductor chips each having an integrated electronic circuit and a plurality of bond pads each adapted to send a signal from the electronic circuit to the outside of the package; forming a multi-layer film which has the same size as the wafer, consists of two non-conductive film layers and a conductive layer, and is formed by forming a conductive layer over a first non-conductive film which is a lower one of the two layers, patterning the conductive layer to form the circuit patterns, and laminating a second non-conductive film on the circuit patterns; attaching the multi-layer film to the wafer by adhesive means in such a manner the bond pad regions defined at the semiconductor chips of the wafer are exposed through the opened portions of the multi-layer film; bonding bond fingers provided at the circuit patterns of the multi-layer film to the bond pads of the semiconductor chips by wires, respectively; covering a sealant layer over the opened portions of the multi-layer film, thereby protecting the wires from external oxidation and erosion; baking the sealant layer in an oven or furnace at a temperature of 150° C. or more; seating solder balls on solder ball lands provided at the multi-layer film, respectively, and reflowing the solder balls in the oven or furnace at a temperature of 200° C. or more, thereby bonding the solder balls to the circuit patterns; cutting the wafer along its street lines using a sawing device so that it can be divided into individual semiconductor chips, thereby forming chip size packages having the same size as their semiconductor chips.
Claim 3
Dependent Claim
24 words
The method in accordance with claim 1, wherein the bond pads are arranged along end portions of the upper surface of each semiconductor chip.
Claim 4
Dependent Claim
25 words
The method in accordance with claim 1, wherein the bond pads are arranged along a central portion of the upper surface of each semiconductor chip.
Claim 5
Dependent Claim
59 words
The method in accordance with claim 1, wherein the second non-conductive film is opened in regions corresponding to solder ball lands where the solder balls are bonded to the circuit patterns and in regions where bond fingers provided at the circuit patterns are disposed so that the bond fingers can be connected to the bond pads by the wires.
Claim 6
Dependent Claim
23 words
The method in accordance with claim 4, wherein the solder ball lands are regularly arranged on an upper surface of the second film.
Claim 7
Dependent Claim
19 words
The method in accordance with claim 1, wherein the conductive layer has a thickness of 20 μm or less.
Claim 8
Dependent Claim
19 words
The method in accordance with claim 1, wherein the adhesive means comprises an epoxy adhesive or an adhesive film.
Claim 9
Dependent Claim
40 words
The method in accordance with claim 1, wherein the sealant layer is made of a polyimide coating solution, or an epoxy encapsulation material and covers the opened portions of the non-conductive film so that the wires can not be exposed.
Claim 10
Dependent Claim
110 words
The method in accordance with claim 1, wherein the solder balls are formed by laying a stencil screen printer having a plurality of through holes respectively corresponding to the solder ball lands on the multi-layer film, disposing solder powder on the stencil screen printer, blading the solder powder by a blade in such a manner that the solder powder is filled in the through holes on the solder ball lands, and reflowing the filled solder powder in the oven or furnace at a temperature of 220° C. or more so that the solder powder can be bonded to the circuit patterns at the solder ball lands while forming solder balls.
Claim 11
Dependent Claim
40 words
The method in accordance with claim 9, wherein the stencil screen printer is provided with grooves at portions of its bottom surface respectively corresponding to regions where the sealant layer is coated, so that the sealant layer can be protected.
Claim 12
Dependent Claim
32 words
The method in accordance with claim 1, wherein the solder balls, which are seated on the solder ball lands, are individually prepared to have a spherical shape prior to the seating step.
Claim 13
Dependent Claim
49 words
The method in accordance with claim 1, further comprising the steps of: coating a flux on the solder ball lands prior to the step of reflowing the solder balls; and conducting a cleaning process to remove unnecessary residue of the flux after completing the reflowing of the solder balls.
Claim 14
Dependent Claim
34 words
The method in accordance with claim 1, wherein a plurality of circuit lines are connected to each circuit pattern so that the circuit pattern can be used as a power bonding or ground bonding.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-11 | 2002-07-13 | 2003-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-11 | 2006-07-13 | 2007-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-11 | 2010-07-13 | 2011-01-12 | $7700.00 | Window Closed / Lapsed |