Processor module with dual-bank SRAM cache having shared capacitors and R-C elements integrated into the module substrate

Claim 2

A dual-bank processor module with a cache memory and shared capacitors comprising: a substrate having wiring traces for conducting signals, the substrate also having power-supply traces and ground traces for connection to a power supply voltage and a ground voltage; a processor chip, mounted on the substrate, for generating addresses for fetching data and instructions; a plurality of leads along a bottom edge of the substrate, the plurality of leads including a power-supply lead and a ground lead and control leads and data leads, the plurality of leads for electrically connecting the dual-bank processor module to a system, the control leads and data leads for fetching data and instructions not found in the cache memory on the substrate; and the cache memory having pairs of static random-access-memory SRAM chips mounted on the substrate, each pair having a first SRAM chip from a first bank and a second SRAM chip from a second bank, each pair of SRAM chips sharing a capacitor coupled between power-supply and ground pins of the first and second SRAM chips, whereby each pair of SRAM chips share a capacitor.

Claim 3

The dual-bank processor module of claim 1 wherein all capacitors are mounted on a first surface of the substrate and no capacitors are mounted on a second surface of the substrate, the second surface opposite the first surface.

Claim 4

The dual-bank processor module of claim 2 wherein the processor chip further comprises processor-de-coupling capacitors formed in a processor package for the processor chip, the processor package mounted on the second surface.

Claim 5

The dual-bank processor module of claim 3 wherein the processor package is a ball-grid-array BGA package having solder balls for connection to the substrate.

Claim 6

The dual-bank processor module of claim 2 wherein each pair of SRAM chips includes the first SRAM chip mounted on the first surface of the substrate and the second SRAM chip mounted on the second surface of the substrate, whereby the SRAM chips in a pair are mounted on opposite surfaces of the substrate.

Claim 7

The dual-bank processor module of claim 5 wherein the first SRAM chip is mounted opposite the second SRAM chip, the first SRAM chip on the first surface overlapping a portion of the second SRAM chip on the second surface, the substrate having an overlapping portion having the first surface with the first SRAM chip mounted thereon and the second surface with a portion of the second SRAM chip mounted thereon.

Claim 8

The dual-bank processor module of claim 2 wherein control leads from the processor chip to the cache memory include a first chip-enable signal and a second chip-enable signal, the first chip-enable signal connected to all SRAM chips in the first bank and not connected to any SRAM chips in the second bank, while the second chip-enable signal is connected to all SRAM chips in the second bank and is not connected to any SRAM chips in the first bank, wherein the first SRAM chip is controlled by the first chip-enable signal and the second SRAM chip is controlled by the second chip-enable signal, whereby the first bank and the second bank of SRAMs are separately controlled.

Claim 9

The dual-bank processor module of claim 7 wherein the first SRAM chip and the second SRAM chip in the pair of SRAM chips both are coupled to a same group of data signals in data leads from the processor chip, the same group of data signals not connected to other SRAM chips in the dual-bank processor module, whereby each pair of SRAM chips is coupled to a unique group of data signals.

Claim 10

The dual-bank processor module of claim 8 further comprising: a notch in the substrate for locking the dual-bank processor module in a socket; a heat sink; holes in the substrate for mounting the heat sink to the substrate, the heat sink thermally connected to the processor chip; whereby the dual-bank processor module is interchangeable with other processor modules.

Claim 11

The dual-bank processor module of claim 4 further comprising: a through-hole in the substrate for each pair of SRAM chips, the through-hole being near the capacitor, the through-hole for connecting the capacitor to the ground pin of the first SRAM chip and to the ground pin of the second SRAM chip, whereby each pair of SRAM chips has a through-hole in the substrate for local connection of ground voltage to the capacitor.

Claim 12

The dual-bank processor module of claim 10 wherein the capacitor is mounted under the first SRAM chip.

Claim 13

The dual-bank processor module of claim 10 wherein the capacitor is mounted adjacent to the first SRAM chip.

Claim 14

The dual-bank processor module of claim 10 wherein the capacitor is formed inside the substrate nearer to the first SRAM chip and to the second SRAM chip than to other SRAM chips in other pairs of SRAM chips.

Claim 15

The dual-bank processor module of claim 10 wherein the substrate having wiring traces for conducting signals comprises: a four-layer printed circuit board (PCB), wherein the power-supply traces and the ground traces are each in a layer which also contains conducting signals, whereby cost is reduced by sharing power and ground layers with the conducting signals.

Claim 16

The dual-bank processor module of claim 14 wherein the plurality of leads along the bottom edge comprise a single-edge-cartridge connector.

Claim 17

The dual-bank processor module of claim 15 wherein the SRAM chips comprise synchronous SRAM chips.

Claim 18

The dual-bank processor module of claim 16 further comprising: dampening resistors mounted on the first surface of the substrate, wherein no resistors are mounted on the second surface of the substrate, the second surface opposite the first surface, whereby resistors are mounted on only one surface of the substrate.

Claim 19

A dual-sided, multi-bank processor module comprising: a substrate for making electrical connection between memory chips mounted on a first surface and on a second surface of the substrate; a processor chip, mounted on the substrate, for generating addresses of data and instructions requested from a cache memory or a main memory; a bus-interface chip, mounted on the substrate and coupled to the processor chip, for controlling a cache-data bus to the processor chip and a main-memory bus; a plurality of external connecting leads on the substrate, the plurality of external connecting leads for connecting to the main memory in a host system, the plurality of connecting leads including data leads and control leads for the main-memory bus controlled by the bus-interface chip; a plurality of shared capacitors for suppressing current spikes, the plurality of capacitors mounted on the first surface but not mounted on the second surface of the substrate; a first bank of memory chips for storing data, the first bank having first memory chips mounted on the substrate, the first bank driving data onto all data bits of the cache-data bus; a second bank of memory chips for storing data, the second bank having second memory chips mounted on the substrate, the second bank driving data onto all data bits of the cache-data bus; wherein the first and the second bank drive the same data bits of the cache-data bus but are controlled by the bus-interface chip to not drive data simultaneously; the plurality of capacitors, the first bank, and the second bank being arranged on the substrate into local groups, each local group having a first memory chip from the first bank and a second memory chip from the second bank and local capacitors, the local capacitors physically located closer to the first and second memory chips in the local group than to other memory chips, whereby the local capacitors in each local group suppressing current spikes generated by the memory chips in the local group when the data in either the first bank or the second bank is accessed.

Claim 20

A dual-sided, multi-bank processor module comprising: a substrate for making electrical connection between memory chips mounted on a first surface and on a second surface of the substrate; a processor chip, mounted on the substrate, for generating addresses of data and instructions requested from a cache memory or a main memory; a bus-interface chip, mounted on the substrate and coupled to the processor chip, for controlling a cache-data bus to the processor chip and a main-memory bus; a plurality of external connecting leads on the substrate, the plurality of external connecting leads for connecting to the main memory in a host system, the plurality of connecting leads including data leads and control leads for the main-memory bus controlled by the bus-interface chip; a plurality of shared capacitors for suppressing current spikes, the plurality of capacitors mounted on the first surface but not mounted on the second surface of the substrate; a first bank of memory chips for storing data, the first bank having first memory chips mounted on the substrate, the first bank driving data onto all data bits of the cache-data bus; a second bank of memory chips for storing data, the second bank having second memory chips mounted on the substrate, the second bank driving data onto all data bits of the cache-data bus; wherein the first and the second bank drive the same data bits of the cache-data bus but are controlled by the bus-interface chip to not drive data simultaneously; the plurality of capacitors, the first bank, and the second bank being arranged on the substrate into local groups, each local group having a first memory chip from the first bank and a second memory chip from the second bank and local capacitors, the local capacitors physically located closer to the first and second memory chips in the local group than to other memory chips, whereby the local capacitors in each local group suppressing current spikes generated by the memory chips in the local group when the data in either the first bank or the second bank is accessed.

Claim 21

The dual-sided, multi-bank processor module of claim 18 wherein the first memory chip is mounted on a surface of the substrate opposite the second memory chip on a different surface of the substrate.

Claim 22

The dual-sided, multi-bank processor module of claim 19 wherein all memory chips in the first bank are mounted on the first surface and all memory chips in the second bank are mounted on the second surface, and wherein the processor chip is mounted on the second surface and the bus-interface chip is mounted on the first surface.

Claim 23

The dual-sided, multi-bank processor module of claim 19 wherein the host system is a personal computer (PC).