US5654929A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Refresh strategy for DRAMs
Assignee: Samsung Electronics Co Ltd
•
Filing: 1995-09-14
•
Granted: 1997-08-05
•
Expires: 2015-09-14
Abstract
Abstract An improved method of accessing dynamic random access memory (DRAM) banks during refresh cycles contemplates sequentially accessing DRAM banks which do not share common filtering capacitors. In this manner, voltage drops caused by refresh accesses are not observed in consecutive clock cycles at the same filtering capacitors so that the filtering capacitors will have sufficient recovery time to restore the supply voltage to the original voltage level before another refresh hit occurs at the same capacitor. In this manner, significant voltage drops are alleviated at the voltage supply inputs to the DRAM banks.
Inventors
- 👤 L. Randall Mote, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 14:35
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/406
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
104 words
A method for refreshing volatile memory banks which share at least one common filtering capacitor used to filter out voltage drops on a voltage supply line, said method comprising the steps of: initiating a refresh of a first memory bank which shares said at least one filtering capacitor in common with a second memory bank; initiating a refresh of a third memory bank which does not share said at least one filtering capacitor with said first and second memory banks after initiating said refresh of said first memory bank; and refreshing said second memory bank after initiating said refresh of said third memory bank.
Claim 2
Independent Claim
104 words
A method for refreshing volatile memory banks which share at least one common filtering capacitor used to filter out voltage drops on a voltage supply line, said method comprising the steps of: initiating a refresh of a first memory bank which shares said at least one filtering capacitor in common with a second memory bank; initiating a refresh of a third memory bank which does not share said at least one filtering capacitor with said first and second memory banks after initiating said refresh of said first memory bank; and refreshing said second memory bank after initiating said refresh of said third memory bank.
Claim 3
Dependent Claim
19 words
A method as defined in claim 1, wherein said first, second and third memory banks are CMOS memory banks.
Claim 4
Dependent Claim
44 words
A method as defined in claim 1, further comprising the step of initiating a refresh of a fourth memory bank subsequent to initiating said refresh of said second memory bank, wherein said fourth memory bank and said third memory bank share another filtering capacitance.
Claim 5
Dependent Claim
17 words
A method as defined in claim 1, wherein each said refresh is a CAS before RAS refresh.
Claim 6
Independent Claim
229 words
A method of reducing supply voltage drops which occur during refreshes to a first memory bank and a second memory bank, said first and second memory banks sharing at least one common capacitor, wherein a supply voltage drop is observed at said first and second memory banks each time a refresh occurs to either said first memory bank or said second memory bank, and wherein the time between refresh cycles is such that immediately successive refreshes to said first and second memory banks would result in a larger supply voltage drop at said first and second memory banks than would a single refresh to either one or the other of said first and second memory banks, said method comprising the steps of: initiating a refresh to said first memory bank which shares said at least one capacitor in common with said second memory bank; and initiating a refresh to said second memory bank after a sufficient number of refresh cycles have been initiated on at least one other memory bank which does not share said at least one capacitor with said first and second memory banks, so that said refresh to said second memory bank does not result in a larger supply voltage drop at said first and second memory banks than would a solitary refresh to either one or the other of said first and second memory banks.
Claim 7
Independent Claim
229 words
A method of reducing supply voltage drops which occur during refreshes to a first memory bank and a second memory bank, said first and second memory banks sharing at least one common capacitor, wherein a supply voltage drop is observed at said first and second memory banks each time a refresh occurs to either said first memory bank or said second memory bank, and wherein the time between refresh cycles is such that immediately successive refreshes to said first and second memory banks would result in a larger supply voltage drop at said first and second memory banks than would a single refresh to either one or the other of said first and second memory banks, said method comprising the steps of: initiating a refresh to said first memory bank which shares said at least one capacitor in common with said second memory bank; and initiating a refresh to said second memory bank after a sufficient number of refresh cycles have been initiated on at least one other memory bank which does not share said at least one capacitor with said first and second memory banks, so that said refresh to said second memory bank does not result in a larger supply voltage drop at said first and second memory banks than would a solitary refresh to either one or the other of said first and second memory banks.
Claim 8
Dependent Claim
18 words
A method as defined in claim 5, wherein said sufficient number of refresh cycles is one refresh cycle.
Claim 9
Dependent Claim
17 words
A method as defined in claim 5, wherein each said refresher is a CAS before RAS refresh.
References Cited (Backward Citations)
US5475645A
Cited
US5500831A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-04 | 2001-02-03 | 2001-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-04 | 2005-02-03 | 2005-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-04 | 2009-02-03 | 2009-08-05 | $7700.00 | Window Closed / Lapsed |