US5504373A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory module
Assignee: Samsung Electronics Co Ltd
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Filing: 1994-05-16
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Granted: 1996-04-02
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Expires: 2014-05-16
Abstract
Abstract A semiconductor memory module is formed of semiconductor packages respectively having at least one defect data line combined to be mounted to a module substrate which has two rows of auxiliary pads for excluding the defect data line of the mounted semiconductor packages from overall data lines of the module to thus attain more than a required memory capacity. By connecting the auxiliary pads with coupling units of resistors or jumper cables to isolate the defect data lines, the semiconductor memory module achieves the required memory capacity and utilizes defective semiconductor packages to reduce manufacturing costs, to attain excellent compatibility resulting from employing all kinds of semiconductor packages, and to simplify the data line connection process. Further, reworking semiconductor package is easy which improves yield, and humid air is prevented from permeating into the interior of the molding resin thereby preventing failures such as disconnection of wires and improving reliability.
Inventors
- 👤 Sang E. Oh
- 👤 Seung K. Mok
- 👤 Gu S. Kim
- 👤 Seung H. Ahn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:09
CPC Classifications
H; H05; H05K; H05K1/00; H05K1/02; H05K1/0286; H05K1/0292; G; G11; G11C; G11C29/00; G11C29/70; G11C29/702; G11C29/72; G11C29/88; H05K2201/00; H05K2201/10; H05K2201/10613; H05K2201/10621; H05K2201/10636; H05K2203/00; H05K2203/17; H05K2203/173; H05K3/00; H05K3/22; H05K3/222; H10; H10W; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W70/682; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20; H10W90/00; H10W90/701; H10W90/751; H10W90/754; Y; Y02; Y02P; Y02P70/00; Y02P70/50
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
161 words
A semiconductor memory module for mounting a plurality of semiconductor packages at respective mounting areas on a module substrate comprising: wiring patterns formed on said module substrate; contact pads electrically connected to said wiring patterns for mounting leads of capacitors functioning to prevent electrical shock during on and off operation of said semiconductor packages; auxiliary pads provided on said module substrate on one side of said mounting areas of said semiconductor packages; a plurality of external I/O pins mounted on said module substrate for electrically connecting end portions of respective of said wiring patterns; semiconductor packages having external leads mounted to be bonded on said contact pads of said module substrate, at least one data I/O line being defective; said memory module having a memory capacity; and coupling means for selectively connecting normal data lines of said module only to those of said auxiliary pads other than any corresponding to any said defective data I/O line of a said semiconductor package.
Claim 2
Dependent Claim
161 words
A semiconductor memory module for mounting a plurality of semiconductor packages at respective mounting areas on a module substrate comprising: wiring patterns formed on said module substrate; contact pads electrically connected to said wiring patterns for mounting leads of capacitors functioning to prevent electrical shock during on and off operation of said semiconductor packages; auxiliary pads provided on said module substrate on one side of said mounting areas of said semiconductor packages; a plurality of external I/O pins mounted on said module substrate for electrically connecting end portions of respective of said wiring patterns; semiconductor packages having external leads mounted to be bonded on said contact pads of said module substrate, at least one data I/O line being defective; said memory module having a memory capacity; and coupling means for selectively connecting normal data lines of said module only to those of said auxiliary pads other than any corresponding to any said defective data I/O line of a said semiconductor package.
Claim 3
Dependent Claim
27 words
A semiconductor memory module as claimed in claim 1, wherein said auxiliary pads are provided in two rows, each forming a right angle to said contact pads.
Claim 4
Dependent Claim
20 words
A semiconductor memory module as claimed in claim 1, wherein said coupling means are resistors soldered between said auxiliary pads.
Claim 5
Dependent Claim
38 words
A semiconductor memory module as claimed in claim 1, wherein said coupling means are jumper cable couplers each composing an external pin-type jumper and a socket-type jumper which are cooperable for electrically connecting respective of said auxiliary pads.
Claim 6
Dependent Claim
26 words
A semiconductor memory as claimed in claim 4, wherein said auxiliary pads are provided in two rows, each forming a right angle from said contact pads.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-02 | 1999-10-02 | 2000-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-02 | 2003-10-02 | 2004-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-02 | 2007-10-02 | 2008-04-02 | $7700.00 | Window Closed / Lapsed |