Analog-to-digital converter having a high sampling frequency

Claim 2

An analog-to-digital converter receiving an analog input voltage to be converted into a digital output signal, comprising: a ladder network of resistors in series between a positive supply terminal and a negative supply terminal, which resistors produce a plurality of reference voltages on the nodes between them, a stage of comparators, each comparing the analog input voltage with a respective one of the reference voltages, a memory stage comprising memory cells, each memory cell having a data input, a data output and a clock input, and receiving the output signal of a respective comparator at its data input, all of the memory cells receiving a clock signal at their clock inputs, a binary encoder which receives the outputs of the memory stage at its input and supplies the digital output signal of the converter, characterized in that each memory cell comprises: N memory flip-flops, a multiplexer, and, a control module, each memory flip-flop having a data input, a data output and a clock input, the multiplexer having N data inputs, one output forming the output of the memory cell, and P control inputs, N and P being related such that N=2 P , the control module having N inputs and P outputs, all of the data inputs of the memory flip-flops being connected together to the data input of the memory cell, the jth memory flip-flop (where j=0 to N-1) receiving at its clock input the clock signal delayed by j*T/N, where T is the period of the clock signal, the data outputs of the N memory flip-flops being connected to the N data inputs of the multiplexer, the multiplexer's P control inputs are connected to the P outputs of the control module, and the control module has each of its N inputs connected to a respective one of the clock inputs of the N flip-flops and has its P outputs arranged such that the multiplexer supplies the output signal of the jth memory flip-flop at its output during each (j+1)th fraction of a period of the length T/N.

Claim 3

An analog-to-digital converter as claimed in claim 1, wherein the memory flip-flops in the memory cells of the memory stage are D flip-flops.

Claim 4

An analog-to-digital converter as claimed in claim 1, wherein the memory flip-flops in the memory cells of the memory stage are flip-flops of the master-slave type.

Claim 5

An analog-to-digital converter as claimed in claim 1 wherein each memory cell comprises only two memory flip-flops, and a multiplexer, each memory flip-flop having a data input, a data output and a clock input, the multiplexer having two data inputs and one control input, the data inputs of the two memory flip-flops being connected to one another and forming the data input of the memory cell, one of the memory flip-flops receiving the clock signal at its clock input and the other memory flip-flop receiving the inverse of said clock signal at its clock input, the data outputs of the two memory flip-flops being connected to respective data inputs of the multiplexer, whose control input receives the clock signal and whose output forms the output of the memory cell.

Claim 6

An analog-to-digital converter receiving an analog input voltage to be converted into a digital output signal, comprising: a ladder network of resistors arranged in series between a positive supply terminal and a negative supply terminal, which resistors produce a plurality of reference voltages on the nodes between them, a stage of comparators, each comparing the analog input voltage with a respective one of the reference voltages, a memory stage comprising memory cells, each memory cell having a data input, a data output and a clock input, and receiving the output signal of a respective comparator at its data input, all of the memory cells receiving a clock signal at their clock inputs, a binary encoder which receives the outputs of the memory stage at its input and supplies the digital output signal of the converter, characterized in that each memory cell comprises two memory flip-flops, and a multiplexer, each memory flip-flop having a data input, a data output and a clock input, the multiplexer having two data inputs and one control input, the data inputs of the two memory flip-flops being connected to one another and forming the data input of the memory cell, one of the memory flip-flops receiving the clock signal at its clock input and the other memory flip-flop receiving the inverse of said clock signal at its clock input, the data outputs of the two memory flip-flops being connected to respective data inputs of the multiplexer, whose control input receives the clock signal and whose output forms the output of the memory cell.

Claim 7

An analog-to-digital converter receiving an analog input voltage to be converted into a digital output signal, comprising: a ladder network of resistors arranged in series between a positive supply terminal and a negative supply terminal, which resistors produce a plurality of reference voltages on the nodes between them, a stage of comparators, each comparing the analog input voltage with a respective one of the reference voltages, a memory stage comprising memory cells, each memory cell having a data input, a data output and a clock input, and receiving the output signal of a respective comparator at its data input, all of the memory cells receiving a clock signal at their clock inputs, a binary encoder which receives the outputs of the memory stage at its input and supplies the digital output signal of the converter, characterized in that each memory cell comprises two memory flip-flops, and a multiplexer, each memory flip-flop having a data input, a data output and a clock input, the multiplexer having two data inputs and one control input, the data inputs of the two memory flip-flops being connected to one another and forming the data input of the memory cell, one of the memory flip-flops receiving the clock signal at its clock input and the other memory flip-flop receiving the inverse of said clock signal at its clock input, the data outputs of the two memory flip-flops being connected to respective data inputs of the multiplexer, whose control input receives the clock signal and whose output forms the output of the memory cell.

Claim 8

An analog-to-digital converter as claimed in claim 5, wherein the memory flip-flops in the memory cells of the memory stage are D flip-flops.

Claim 9

An analog-to-digital converter as claimed in claim 5, wherein the memory flip-flops in the memory cells of the memory stage are flip-flops of the master-slave type.

Claim 10

An analog-to-digital converter receiving an analog input voltage to be converted into a digital output signal, comprising: a ladder network of resistors arranged in series between a positive supply terminal and a negative supply terminal, which resistors produce a plurality of reference voltages on the nodes between them, a plurality of folding stages, each comprising an array of comparators adapted to generate a folding signal which varies as a quasi-sinusoidal function of the analog input voltage, and a signal which is the counterpart of said folding signal, a first and a second interpolation stage, the first one receiving the folding signals and the second one receiving their counterparts, each interpolation stage being made up of impedance elements, preferably resistors of equal value, arranged as a divider bridge such that the sampling signals generated across the elements of the first interpolation represent fractions of the folding signals, the signals generated by the second interpolation stage forming their counterparts, a cycle detector which receives the folding signals and their counterparts and supplies cycle pointer signals and signals forming the counterparts thereof, enabling identification of that one of the cycles of the sampling signals which is significative of the value of the analog input voltage, a first memory stage comprising memory cells, each memory cell having two data inputs, a data output and a clock input, and receiving at its data inputs a sampling signal and its counterpart, all of the memory cells forming the first memory stage receiving a clock signal at their clock inputs, a second memory stage comprising memory cells, each memory cell receiving at its data inputs a cycle pointer signal and its counterpart, all of the memory cells forming the second memory stage receiving the clock signal at their clock inputs, a binary encoder which receives the outputs of the memory stages at its input and supplies the digital output signal of the converter, characterized in that the memory cells of the memory stages each comprise: N memory flip-flops, a multiplexer, and, a control module, each memory flip-flop having a data input, a data output and a clock input, the multiplexer having N data inputs and P control inputs and one output forming the output of the memory cell, N and P being related in such a manner that N=2 P , the memory module having N inputs and P outputs, all of the data inputs of the memory flip-flops being connected together to the output of the input comparator of the memory cell, the jth memory flip-flop (where j=0 to N-1) receiving at its clock input the clock signal delayed by j*T/N, where T is the period of the clock signal, the data outputs of the N memory flip-flops being connected to the N data inputs of the multiplexer, the multiplexer's P control inputs are connected to the P outputs of the control module, each of the N inputs of the control module being connected to one of the clock inputs of the N memory flip-flops, and, the P outputs of said control module being arranged such that the multiplexer supplies the output signal of the jth memory flip-flop at its output during each (j+1)th fraction of a period of the length T/N.

Claim 11

An analog-to-digital converter receiving an analog input voltage to be converted into a digital output signal, comprising: a ladder network of resistors arranged in series between a positive supply terminal and a negative supply terminal, which resistors produce a plurality of reference voltages on the nodes between them, a plurality of folding stages, each comprising an array of comparators adapted to generate a folding signal which varies as a quasi-sinusoidal function of the analog input voltage, and a signal which is the counterpart of said folding signal, a first and a second interpolation stage, the first one receiving the folding signals and the second one receiving their counterparts, each interpolation stage being made up of impedance elements, preferably resistors of equal value, arranged as a divider bridge such that the sampling signals generated across the elements of the first interpolation represent fractions of the folding signals, the signals generated by the second interpolation stage forming their counterparts, a cycle detector which receives the folding signals and their counterparts and supplies cycle pointer signals and signals forming the counterparts thereof, enabling identification of that one of the cycles of the sampling signals which is significative of the value of the analog input voltage, a first memory stage comprising memory cells, each memory cell having two data inputs, a data output and a clock input, and receiving at its data inputs a sampling signal and its counterpart, all of the memory cells forming the first memory stage receiving a clock signal at their clock inputs, a second memory stage comprising memory cells, each memory cell receiving at its data inputs a cycle pointer signal and its counterpart, all of the memory cells forming the second memory stage receiving the clock signal at their clock inputs, a binary encoder which receives the outputs of the memory stages at its input and supplies the digital output signal of the converter, characterized in that the memory cells of the memory stages each comprise: N memory flip-flops, a multiplexer, and, a control module, each memory flip-flop having a data input, a data output and a clock input, the multiplexer having N data inputs and P control inputs and one output forming the output of the memory cell, N and P being related in such a manner that N=2 P , the memory module having N inputs and P outputs, all of the data inputs of the memory flip-flops being connected together to the output of the input comparator of the memory cell, the jth memory flip-flop (where j=0 to N-1) receiving at its clock input the clock signal delayed by j*T/N, where T is the period of the clock signal, the data outputs of the N memory flip-flops being connected to the N data inputs of the multiplexer, the multiplexer's P control inputs are connected to the P outputs of the control module, each of the N inputs of the control module being connected to one of the clock inputs of the N memory flip-flops, and, the P outputs of said control module being arranged such that the multiplexer supplies the output signal of the jth memory flip-flop at its output during each (j+1)th fraction of a period of the length T/N.

Claim 12

An analog-to-digital converter as claimed in claim 8, wherein the memory flip-flops in the memory cells of the memory stage are D flip-flops.

Claim 13

An analog-to-digital converter as claimed in claim 8, wherein the memory flip-flops in the memory cells of the memory stage are flip-flops of the master-slave type.

Claim 14

An analog-to-digital converter as claimed in claim 8, wherein N is equal to two, and P is equal to one.

Claim 15

An analog-to-digital converter as claimed in claim 11, wherein the memory flip-flops in the memory cells of the memory stage are D flip-flops.

Claim 16

An analog-to-digital converter as claimed in claim 11, wherein the memory flip-flops in the memory cells of the memory stage are flip-flops of the master-slave type.

Claim 17

An analog-to-digital converter as claimed in claim 8 wherein each memory cell comprises only two memory flip-flops, and a multiplexer, each memory flip-flop having a data input, a data output and a clock input, the multiplexer having two data inputs and one control input, the data inputs of the two memory flip-flops being connected to one another and forming the data input of the memory cell, one of the memory flip-flops receiving the clock signal at its clock input and the other memory flip-flop receiving the inverse of said clock signal at its clock input, the data outputs of the two memory flip-flops being connected to respective data inputs of the multiplexer, whose control input receives the clock signal and whose output forms the output of the memory cell.

Claim 18

A memory cell having a data input, a data output and a clock input which receives a clock signal, characterized in that the memory cell comprises: N memory flip-flops, a multiplexer, and, a control module, each memory flip-flop having a data input, a data output and a clock input, the multiplexer having N data inputs, an output forming the output of the memory cell, and P control inputs, N and P being related such that N=2 P , the control module having N inputs and P outputs, all of the data inputs of the memory flip-flops being connected together to the data input of the memory cell, the jth memory flip-flop (where j=0 to N-1) receiving at its clock input the clock signal delayed by j*T/N, where T is the period of the clock signal, the data outputs of the N memory flip-flops being connected to respective N data inputs of the multiplexer, the multiplexer's P control inputs are connected to the P outputs of the control module, and the control module has its N inputs connected to respective ones of the clock inputs of the N flip-flops and has its P outputs arranged such that the multiplexer supplies the output signal of the jth memory flip-flop at its output during each (j+1)th fraction of a period of the length T/N.

Claim 19

A memory cell having a data input, a data output and a clock input which receives a clock signal, characterized in that the memory cell comprises: N memory flip-flops, a multiplexer, and, a control module, each memory flip-flop having a data input, a data output and a clock input, the multiplexer having N data inputs, an output forming the output of the memory cell, and P control inputs, N and P being related such that N=2 P , the control module having N inputs and P outputs, all of the data inputs of the memory flip-flops being connected together to the data input of the memory cell, the jth memory flip-flop (where j=0 to N-1) receiving at its clock input the clock signal delayed by j*T/N, where T is the period of the clock signal, the data outputs of the N memory flip-flops being connected to respective N data inputs of the multiplexer, the multiplexer's P control inputs are connected to the P outputs of the control module, and the control module has its N inputs connected to respective ones of the clock inputs of the N flip-flops and has its P outputs arranged such that the multiplexer supplies the output signal of the jth memory flip-flop at its output during each (j+1)th fraction of a period of the length T/N.

Claim 20

A memory cell as claimed in claim 15, wherein its memory flip-flops are D flip-flops.

Claim 21

A memory cell as claimed in claim 15, wherein its memory flip-flops are flip-flops of the master-slave type.

Claim 22

A memory cell as claimed in claim 15, wherein N is equal to two, and P is equal to one.

Claim 23

A memory cell as claimed in claim 18, wherein its memory flip-flops are D flip-flops.

Claim 24

A memory cell as claimed in claim 18, wherein its memory flip-flops are flip-flops of the master-slave type.

Claim 25

A memory cell as claimed in claim 15 which comprises only two memory flip-flops, and a multiplexer, each memory flip-flop having a data input, a data output and a clock input, the multiplexer having two data inputs and one control input, the data inputs of the two memory flip-flops being connected to one another and forming the data input of the memory cell, one of the memory flip-flops receiving the clock signal at its clock input and the other memory flip-flop receiving the inverse of said clock signal at its clock input, the data outputs of the two memory flip-flops being connected to respective data inputs of the multiplexer, whose control input receives the clock signal and whose output forms the output of the memory cell.