Patent US6295646B1 successfully refreshed from Google Patents.
US4211999A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Converter for converting a high frequency video signal to a digital signal
Assignee: United States Department of the Navy
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Filing: 1977-11-23
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Granted: 1980-07-08
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Expires: 1997-11-23
Abstract
Abstract A converter for converting a high frequency video input signal to a digital signal by detecting the peak voltages of the input signal. A video input signal fans out to a plurality of comparators of which each are connected to a resistive ladder of equal resistors values. One end of the resistive ladder is connected with a positive reference voltage and the other end is connected with a negative reference voltage. Real time is divided into sampling bins determined by the cycle time of a clock and, within each bin, the digital output from a plurality of master-slave flip-flops shows the maximum level reached by the video input signal. The outputs from the flip-flops go to a pair of priority encoders and a multiplexer for indicating in digital form the highest point reached on the resistive ladder.
Inventors
- 👤 Ronald L. Clark
- 👤 John L. Kreeger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:47
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/36; H03M1/361; H03M1/362; H03M1/365
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
243 words
A high speed peak-detecting analog-to-digital converter comprising, an analog voltage signal, a plurality of voltage comparators each having an output terminal and having an input connected to said analog voltage signal, first means for providing a different threshold voltage to each said comparator, each said comparator providing an output signal at said output terminal whenever the voltage value of said analog voltage signal exceeds said threshold voltage being applied to a particular comparator, clock pulse generating means, second means connected with said output terminals and triggered by said clock pulse generating means for continuously sampling said analog voltage signal and providing an output signal for each comparator whose threshold voltage is lower than the voltage value of the sampled analog voltage signal, first and second priority encoders connected with said second means for encoding each threshold voltage which is lower in value than the voltage value of the sampled analog voltage signal and providing a digital output denoting the highest threshold voltage which was exceeded by the sampled analog voltage, and a multiplexer connected with said first and second priority encoders for accepting the digital output of said first priority encoder when said second priority encoder does not provide a digital output and for accepting only the digital output of said second priority encoder when said second priority encoder provides an output and providing a digital output which is representative of the highest threshold voltage which was exceeded by the sampled analog voltage.
Claim 2
Dependent Claim
243 words
A high speed peak-detecting analog-to-digital converter comprising, an analog voltage signal, a plurality of voltage comparators each having an output terminal and having an input connected to said analog voltage signal, first means for providing a different threshold voltage to each said comparator, each said comparator providing an output signal at said output terminal whenever the voltage value of said analog voltage signal exceeds said threshold voltage being applied to a particular comparator, clock pulse generating means, second means connected with said output terminals and triggered by said clock pulse generating means for continuously sampling said analog voltage signal and providing an output signal for each comparator whose threshold voltage is lower than the voltage value of the sampled analog voltage signal, first and second priority encoders connected with said second means for encoding each threshold voltage which is lower in value than the voltage value of the sampled analog voltage signal and providing a digital output denoting the highest threshold voltage which was exceeded by the sampled analog voltage, and a multiplexer connected with said first and second priority encoders for accepting the digital output of said first priority encoder when said second priority encoder does not provide a digital output and for accepting only the digital output of said second priority encoder when said second priority encoder provides an output and providing a digital output which is representative of the highest threshold voltage which was exceeded by the sampled analog voltage.
Claim 3
Dependent Claim
24 words
A high speed peak-detecting analog-to-digital converter as set forth in claim 1 wherein said first means is a voltage divider having substantially linear characteristics.
Claim 4
Dependent Claim
26 words
A high speed peak-detecting analog-to-digital converter as set forth in claim 1 having means for indicating that the highest threshold voltage level provided is too low.
Claim 5
Dependent Claim
242 words
A high speed peak detecting analog-to-digital converter comprising, an analog voltage signal to be converted to digital form, a voltage divider having a plurality of series connected resistors for providing a plurality of threshold voltages, a plurality of comparators equal in number to the number of resistors of said voltage divider each having first and second input terminals, each said comparator having one input terminal connected to said analog voltage signal and the other said input terminal connected to one end of a different resistor in said voltage divider, a plurality of master-slave flip-flops connected one each to an output of said comparators, clock pulse generating means for triggering said master-slave flip-flops to continuously sample said analog voltage signal, first and second priority encoders connected with said plurality of master-slave flip-flops for encoding each threshold voltage which is lower in value than the voltage value of the sampled analog voltage signal and providing a digital output denoting the highest threshold voltage which was exceeded by the sampled analog voltage, and a multiplexer connected with said first and second priority encoders for accepting the digital output of said first priority encoder when said second priority encoder does not provide a digital output and for accepting only the digital output of said second priority encoder when said second priority encoder provides an output and providing a digital output which is representative of the highest threshold voltage which was exceeded by the sampled analog voltage.
Claim 6
Dependent Claim
242 words
A high speed peak detecting analog-to-digital converter comprising, an analog voltage signal to be converted to digital form, a voltage divider having a plurality of series connected resistors for providing a plurality of threshold voltages, a plurality of comparators equal in number to the number of resistors of said voltage divider each having first and second input terminals, each said comparator having one input terminal connected to said analog voltage signal and the other said input terminal connected to one end of a different resistor in said voltage divider, a plurality of master-slave flip-flops connected one each to an output of said comparators, clock pulse generating means for triggering said master-slave flip-flops to continuously sample said analog voltage signal, first and second priority encoders connected with said plurality of master-slave flip-flops for encoding each threshold voltage which is lower in value than the voltage value of the sampled analog voltage signal and providing a digital output denoting the highest threshold voltage which was exceeded by the sampled analog voltage, and a multiplexer connected with said first and second priority encoders for accepting the digital output of said first priority encoder when said second priority encoder does not provide a digital output and for accepting only the digital output of said second priority encoder when said second priority encoder provides an output and providing a digital output which is representative of the highest threshold voltage which was exceeded by the sampled analog voltage.
Claim 7
Dependent Claim
21 words
A high speed peak-detecting analog-to-digital converter as set forth in claim 4 wherein said voltage divider has a substantially linear characteristic.
Claim 8
Dependent Claim
23 words
A high speed peak-detecting analog-to-digital converter as set forth in claim 4 having means for applying a constant voltage across said voltage divider.
Claim 9
Dependent Claim
26 words
A high speed peak-detecting analog-to-digital converter as set forth in claim 4 having means for indicating that the highest threshold voltage level provided is too low.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-07-08 | 1984-01-07 | 1984-07-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-07-08 | 1988-01-07 | 1988-07-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-07-08 | 1992-01-07 | 1992-07-08 | $7700.00 | Window Closed / Lapsed |