US5856232A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating T-shaped electrode and metal layer having low resistance
Assignee: Pendragon Electronics and Telecommunications Research LLC
•
Filing: 1996-07-05
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Granted: 1999-01-05
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Expires: 2016-07-05
Abstract
Abstract A method for fabricating a T-shaped gate electrode includes the steps of: forming a fine gate pattern on a semiconductor substrate; forming an insulating layer on the semiconductor substrate on which the gate pattern is formed, and forming a planarizing layer on the insulating layer to planarize the surface of the semiconductor substrate; etching the planarizing layer to expose the top of the insulating layer; isotropically etching the insulating layer to expose the gate pattern using the planarizing layer as a mask; etching the exposed gate pattern to selectively expose the semiconductor substrate; depositing a gate metal to cover the exposed substrate, the insulating layer and the planarizing layer, to form a T-shaped gate; and simultaneously removing the planarizing layer, thereby forming a T-shaped gate metal with improved productivity.
Inventors
- 👤 Jeon-Wook Yang
- 👤 Eung-Gee Oh
- 👤 Byung-Sun Park
- 👤 Chul-Sun Park
- 👤 Kwang-Eui Pyun
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:12
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/012; H10D64/0124; H10D64/0125; Y; Y10; Y10S; Y10S148/00; Y10S148/10
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
130 words
A method for fabricating a T-shaped gate electrode, comprising the steps of: forming a fine gate pattern on a semiconductor substrate; forming an insulating layer on said semiconductor substrate on which said gate pattern is formed, and forming a planarizing layer on said insulating layer to planarize the surface of said semiconductor substrate; etching said planarizing layer to expose the top of said insulating layer; isotropically etching said insulating layer to expose said gate pattern using said remaining planarizing layer as a mask; etching said exposed gate pattern to selectively expose said semiconductor substrate; depositing a gate metal to cover said exposed substrate, said insulating layer and said planarizing layer, to form a T-shaped gate; and removing said planarizing layer to lift off the metal deposited on said planarizing layer.
Claim 2
Independent Claim
130 words
A method for fabricating a T-shaped gate electrode, comprising the steps of: forming a fine gate pattern on a semiconductor substrate; forming an insulating layer on said semiconductor substrate on which said gate pattern is formed, and forming a planarizing layer on said insulating layer to planarize the surface of said semiconductor substrate; etching said planarizing layer to expose the top of said insulating layer; isotropically etching said insulating layer to expose said gate pattern using said remaining planarizing layer as a mask; etching said exposed gate pattern to selectively expose said semiconductor substrate; depositing a gate metal to cover said exposed substrate, said insulating layer and said planarizing layer, to form a T-shaped gate; and removing said planarizing layer to lift off the metal deposited on said planarizing layer.
Claim 3
Dependent Claim
33 words
The method as claimed in claim 1, wherein the width of an upper part of said T-shaped gate is controlled by varying the sidewall thickness of said insulating layer on said gate pattern.
Claim 4
Independent Claim
109 words
A method for fabricating a T-shaped metal layer having a low resistance, comprising the steps of: forming a fine gate metal on a semiconductor substrate; forming an insulating layer on said semiconductor substrate on which said fine gate metal is formed; forming a planarizing layer on said insulating layer, and etching said planarizing layer to selectively expose said insulating layer; etching the exposed portion of said insulating layer to expose said fine gate metal, and depositing a metal having a low resistance on the exposed gate metal, said insulating layer and said planarizing layer; and removing said planarizing layer to lift off the metal deposited on said planarizing layer.
Claim 5
Independent Claim
109 words
A method for fabricating a T-shaped metal layer having a low resistance, comprising the steps of: forming a fine gate metal on a semiconductor substrate; forming an insulating layer on said semiconductor substrate on which said fine gate metal is formed; forming a planarizing layer on said insulating layer, and etching said planarizing layer to selectively expose said insulating layer; etching the exposed portion of said insulating layer to expose said fine gate metal, and depositing a metal having a low resistance on the exposed gate metal, said insulating layer and said planarizing layer; and removing said planarizing layer to lift off the metal deposited on said planarizing layer.
References Cited (Backward Citations)
US4965218A
Cited
US4839304A
Cited
JPS63287021A
Cited
US5030589A
Cited
US4980316A
Cited
GB2222308A
Cited
US5032541A
Cited
US4959326A
Cited
JPH0684954A
Cited
US5278083A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-04 | 2002-07-06 | 2003-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-04 | 2006-07-06 | 2007-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-04 | 2010-07-06 | 2011-01-05 | $7700.00 | Window Closed / Lapsed |