US5278083A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for making reliable connections to small features of integrated circuits
Assignee: Texas Instruments Inc
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Filing: 1992-10-16
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Granted: 1994-01-11
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Expires: 2012-10-16
Abstract
Abstract Generally, and in one form of the invention, a method is disclosed for contacting a feature on an integrated circuit comprising: depositing a removable planarizing material 14 around the feature 10 so that a portion of the feature 10 extends above the removable planarizing material 14; depositing a masking layer 18 above the removable planarizing material 14, the masking layer 18 covering all but an exposed region above the feature 10 and an area around the feature; depositing an interconnect contact material 20 on the exposed region; and removing the masking layer 18 and the removable planarizing material 14, leaving the interconnect contact material 20 deposited on the exposed region, whereby a reliable, low capacitance, electrical contact is made to a very small feature 10.
Inventors
- 👤 Darrell G. Hill
- 👤 William U. Liu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:25
CPC Classifications
B; B82; B82Y; B82Y10/00; H; H10; H10W; H10W20/00; H10W20/40; Y; Y10; Y10S; Y10S148/00; Y10S148/011
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
102 words
A method for contacting a feature on an integrated circuit comprising: forming a removable planarizing material around said feature so that a portion of said feature extends above said removable planarizing material; depositing a masking layer above said removable planarizing material, said masking layer covering all but an exposed region above said feature and an area around said feature; depositing an interconnect contact material on said exposed region; and removing said masking layer and said removable planarizing material, leaving said interconnect contact material deposited on said exposed region, whereby a reliable, low capacitance, electrical contact is made to a very small feature.
Claim 2
Independent Claim
102 words
A method for contacting a feature on an integrated circuit comprising: forming a removable planarizing material around said feature so that a portion of said feature extends above said removable planarizing material; depositing a masking layer above said removable planarizing material, said masking layer covering all but an exposed region above said feature and an area around said feature; depositing an interconnect contact material on said exposed region; and removing said masking layer and said removable planarizing material, leaving said interconnect contact material deposited on said exposed region, whereby a reliable, low capacitance, electrical contact is made to a very small feature.
Claim 3
Dependent Claim
23 words
The method of claim 1 further comprising depositing a thin layer of dielectric prior to said step of depositing said removable planarizing material.
Claim 4
Dependent Claim
15 words
The method of claim 2 wherein said dielectric has a thickness of approximately 1000 Angstroms.
Claim 5
Dependent Claim
23 words
The method of claim 3 wherein said dielectric is taken from a group consisting of SiO 2 and Si 3 N 4 .
Claim 6
Dependent Claim
12 words
The method of claim 1 wherein said removable planarizing material is photoresist.
Claim 7
Dependent Claim
11 words
The method of claim 1 wherein said masking material is photoresist.
Claim 8
Dependent Claim
47 words
The method of claim 1 further comprising depositing a conductive material to cover said removable planarizing material and said portion of said feature that extends above said planarizing material prior to depositing said masking layer, and wherein said interconnect contact material is deposited by a plating process.
Claim 9
Dependent Claim
12 words
The method of claim 1 wherein said interconnect contact material is Au.
Claim 10
Independent Claim
72 words
A method for contacting a mesa of a heterojunction bipolar transistor comprising: forming a removable planarizing material around said mesa with a portion of said mesa extending above said removable planarizing material; depositing a photoresist layer on top of said removable planarizing material, said photoresist layer having openings overlapping said mesa in an interconnect pattern; depositing an interconnect contact material in said openings; removing said photoresist; and removing said removable planarizing material.
Claim 11
Independent Claim
72 words
A method for contacting a mesa of a heterojunction bipolar transistor comprising: forming a removable planarizing material around said mesa with a portion of said mesa extending above said removable planarizing material; depositing a photoresist layer on top of said removable planarizing material, said photoresist layer having openings overlapping said mesa in an interconnect pattern; depositing an interconnect contact material in said openings; removing said photoresist; and removing said removable planarizing material.
Claim 12
Dependent Claim
23 words
The method of claim 9 further comprising depositing a thin layer of dielectric prior to said step of depositing said removable planarizing material.
Claim 13
Dependent Claim
15 words
The method of claim 10 wherein said dielectric has a thickness of approximately 1000 Angstroms.
Claim 14
Dependent Claim
23 words
The method of claim 11 wherein said dielectric is taken from a group consisting of SiO 2 and Si 3 N 4 .
Claim 15
Dependent Claim
11 words
The method of claim 9 wherein said planarizing material is photoresist.
Claim 16
Dependent Claim
48 words
The method of claim 9 further comprising depositing a conductive material to cover said removable planarizing material and said portion of said emitter mesa that extends above said planarizing material prior to depositing said photoresist layer, and wherein said interconnect contact material is deposited by a plating process.
Claim 17
Independent Claim
98 words
A method for fabricating an integrated circuit comprising the steps of: (a) removing portions of a semiconductor layer to form a mesa extending above a semiconductor surface; (b) forming a removable planarizing material around said mesa so that a portion of said mesa extends above said removable planarizing material; (c) depositing a masking layer above said removable planarizing material, said masking layer covering all but an exposed region above said feature and an area around said feature; (d) depositing an interconnect contact material on said exposed region; and (e) removing said masking layer and said removable planarizing material.
Claim 18
Independent Claim
98 words
A method for fabricating an integrated circuit comprising the steps of: (a) removing portions of a semiconductor layer to form a mesa extending above a semiconductor surface; (b) forming a removable planarizing material around said mesa so that a portion of said mesa extends above said removable planarizing material; (c) depositing a masking layer above said removable planarizing material, said masking layer covering all but an exposed region above said feature and an area around said feature; (d) depositing an interconnect contact material on said exposed region; and (e) removing said masking layer and said removable planarizing material.
Claim 19
Dependent Claim
35 words
The method of claim 15 wherein said interconnect contact material overhangs a vertical edge of said mesa and extends beyond said vertical edge to form a surface parallel to, but separated from, said semiconductor layer.
Claim 20
Dependent Claim
37 words
The method of claim 16 further comprising depositing metal in the vicinity of said mesa such that said metal lies between said semiconductor layer and said surface that is parallel to, but separated from, said semiconductor layer.
Claim 21
Dependent Claim
15 words
The method claim 17 further comprising depositing a layer of dielectric to cover said metal.
Claim 22
Dependent Claim
32 words
The method of claim 16 wherein a gap region between said semiconductor layer and said surface of said interconnect material that is parallel to, but separated from, said semiconductor layer comprises air.
Claim 23
Dependent Claim
47 words
The method of claim 15 further comprising depositing a conductive material to cover said removable planarizing material and said portion of said feature that extends above said planarizing material prior to depositing said masking layer, and wherein said interconnect contact material is deposited by a plating process.
References Cited (Backward Citations)
JPH01144681A
Cited
JPH01189167A
Cited
JPH01189163A
Cited
JPH02116135A
Cited
US4954457A
Cited
US5166083A
Cited
EP0507434A2
Cited
US5168071A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-10 | 1997-07-12 | 1998-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-10 | 2001-07-12 | 2002-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-10 | 2005-07-12 | 2006-01-11 | $7700.00 | Window Closed / Lapsed |