Low mask count CMOS process with inverse-T gate LDD structure

Claim 1

A method for fabricating a complementary metal-oxide-semiconductor CMOS device with an inverse-T gate LDD structure, the method comprising: forming a first photoresist-mask over a substrate, wherein said first photoresist-mask leaves uncovered portions of said substrate defining a first field oxide (FOX) region, a second FOX region and a third FOX region; forming said first field oxide (FOX) region, said second FOX region and said third FOX region in and on said portions of said substrate left uncovered by said first photoresist-mask removing said first photoresist-mask; forming a first oxide layer on said substrate and between said field oxide regions; forming a first dielectric layer over said first gate oxide layer and on said field oxide regions; forming a second photoresist-mask over said substrate, wherein said second photoresist-mask covers a portion of said substrate between said second and third FOX regions and does not cover a portion of said substrate between said first and second FOX regions; forming a first conductivity-well region in said portion of said substrate left uncovered by said second photoresist-mask; forming a second dielectric layer over said portion of said substrate left uncovered by said second photoresist-mask; removing said second photoresist-mask while leaving said second dielectric layer intact; forming a second conductivity-well region in a portion of said substrate left uncovered by said second dielectric layer; removing said second dielectric layer; removing said first dielectric layer; removing said first oxide layer; forming a second oxide layer on said substrate and between said field oxide regions; forming a first conductive layer over said second oxide layer; forming a third photoresist-mask over said first conductive layer, wherein said third photoresist-mask covers portions of said first conductive layer defining a first gate-structure over said first conductivity-well region and a second gate-structure over said second conductivity-well region; a removing portions of said first conductive layer uncovered by said third photoresist-mask; conformally forming a second conductive layer on said first and second gate-structures, wherein portions of said second conductive layer are on sidewalls of said first and second gate-structures; forming a fourth photoresist-mask over said second conductive layer, wherein said fourth photoresist-mask covers said second conductivity-well region; forming second conductivity-lightly-doped source/drain regions in portions of said first conductivity-well region that are not covered by said first gate-structure, said portions of said second conductive layer on said sidewalls of said first gate-structure, and said first and second FOX regions; forming a third dielectric layer over said second conductive layer; removing portions of said third dielectric layer and said second conductive layer to form first spacers on said sidewalls of said first gate-structure; forming second conductivity heavily-doped source/drain regions in portions of said first conductivity-well region that are not covered by said first gate-structure, said first spacers and said first and second FOX regions; forming a fourth dielectric layer over a portion of said substrate not covered by said fourth photoresist-mask, wherein said first conductivity-well region is covered by said fourth dielectric layer; removing said fourth photoresist-mask while leaving said fourth dielectric layer intact; forming first conductivity-lightly-doped source/drain regions in portions of said second conductivity-well region that are not covered by said second gate-structure, said portions of said second conductive layer on said sidewalls of said second gate-structure, and said second and third FOX regions; forming a fifth dielectric layer over a portion of said second conductive layer covering said second gate-structure; removing portions of said fifth dielectric layer and said second conductive layer to form second spacers on said sidewalls of said second gate-structure; forming first conductivity heavily-doped source/drain regions in portions of said second conductivity-well region that are not covered by said second gate-structure, said second spacers and said second and third FOX regions; forming a sixth dielectric layer on a portion of said substrate not covered by said fourth dielectric layer, wherein said second conductivity-well region is covered by said sixth dielectric layer; forming a seventh dielectric layer on said sixth dielectric layer and said fourth dielectric layer; planarizing said seventh dielectric layer; forming a fifth photoresist-mask over said seventh dielectric layer, wherein portions of said seventh dielectric layer left uncovered by said fifth photoresist-mask define contact windows; removing portions of said second oxide layer, said fourth dielectric layer, said sixth dielectric layer and said seventh dielectric layer not covered by said fifth photoresist-mask to form contact holes; forming a third conductive layer on said seventh dielectric layer and in said contact holes; forming a sixth photoresist-mask over said third conductive layer, wherein portions of said third conductive layer covered by said sixth photoresist-mask define contacts; and removing portions of said third conductive layer not covered by said sixth photoresist-mask.

Claim 2

A method for fabricating a complementary metal-oxide-semiconductor CMOS device with an inverse-T gate LDD structure, the method comprising: forming a first photoresist-mask over a substrate, wherein said first photoresist-mask leaves uncovered portions of said substrate defining a first field oxide (FOX) region, a second FOX region and a third FOX region; forming said first field oxide (FOX) region, said second FOX region and said third FOX region in and on said portions of said substrate left uncovered by said first photoresist-mask removing said first photoresist-mask; forming a first oxide layer on said substrate and between said field oxide regions; forming a first dielectric layer over said first gate oxide layer and on said field oxide regions; forming a second photoresist-mask over said substrate, wherein said second photoresist-mask covers a portion of said substrate between said second and third FOX regions and does not cover a portion of said substrate between said first and second FOX regions; forming a first conductivity-well region in said portion of said substrate left uncovered by said second photoresist-mask; forming a second dielectric layer over said portion of said substrate left uncovered by said second photoresist-mask; removing said second photoresist-mask while leaving said second dielectric layer intact; forming a second conductivity-well region in a portion of said substrate left uncovered by said second dielectric layer; removing said second dielectric layer; removing said first dielectric layer; removing said first oxide layer; forming a second oxide layer on said substrate and between said field oxide regions; forming a first conductive layer over said second oxide layer; forming a third photoresist-mask over said first conductive layer, wherein said third photoresist-mask covers portions of said first conductive layer defining a first gate-structure over said first conductivity-well region and a second gate-structure over said second conductivity-well region; a removing portions of said first conductive layer uncovered by said third photoresist-mask; conformally forming a second conductive layer on said first and second gate-structures, wherein portions of said second conductive layer are on sidewalls of said first and second gate-structures; forming a fourth photoresist-mask over said second conductive layer, wherein said fourth photoresist-mask covers said second conductivity-well region; forming second conductivity-lightly-doped source/drain regions in portions of said first conductivity-well region that are not covered by said first gate-structure, said portions of said second conductive layer on said sidewalls of said first gate-structure, and said first and second FOX regions; forming a third dielectric layer over said second conductive layer; removing portions of said third dielectric layer and said second conductive layer to form first spacers on said sidewalls of said first gate-structure; forming second conductivity heavily-doped source/drain regions in portions of said first conductivity-well region that are not covered by said first gate-structure, said first spacers and said first and second FOX regions; forming a fourth dielectric layer over a portion of said substrate not covered by said fourth photoresist-mask, wherein said first conductivity-well region is covered by said fourth dielectric layer; removing said fourth photoresist-mask while leaving said fourth dielectric layer intact; forming first conductivity-lightly-doped source/drain regions in portions of said second conductivity-well region that are not covered by said second gate-structure, said portions of said second conductive layer on said sidewalls of said second gate-structure, and said second and third FOX regions; forming a fifth dielectric layer over a portion of said second conductive layer covering said second gate-structure; removing portions of said fifth dielectric layer and said second conductive layer to form second spacers on said sidewalls of said second gate-structure; forming first conductivity heavily-doped source/drain regions in portions of said second conductivity-well region that are not covered by said second gate-structure, said second spacers and said second and third FOX regions; forming a sixth dielectric layer on a portion of said substrate not covered by said fourth dielectric layer, wherein said second conductivity-well region is covered by said sixth dielectric layer; forming a seventh dielectric layer on said sixth dielectric layer and said fourth dielectric layer; planarizing said seventh dielectric layer; forming a fifth photoresist-mask over said seventh dielectric layer, wherein portions of said seventh dielectric layer left uncovered by said fifth photoresist-mask define contact windows; removing portions of said second oxide layer, said fourth dielectric layer, said sixth dielectric layer and said seventh dielectric layer not covered by said fifth photoresist-mask to form contact holes; forming a third conductive layer on said seventh dielectric layer and in said contact holes; forming a sixth photoresist-mask over said third conductive layer, wherein portions of said third conductive layer covered by said sixth photoresist-mask define contacts; and removing portions of said third conductive layer not covered by said sixth photoresist-mask.

Claim 32

A method for fabricating a complementary metal-oxide-semiconductor CMOS device with no more than six photoresist-masks, the method comprising: forming field oxide regions in a substrate using a first photoresist-mask to define said field oxide regions; forming a first dielectric layer over said substrate; forming a first conductivity-well region in a portion of said substrate using a second photoresist-mask as an implant mask; forming a second dielectric layer over said first conductivity-well region, said second dielectric layer including no photoresist material; removing said second photoresist-mask while leaving said second dielectric layer intact; forming a second conductivity-well region in a portion of said substrate using said second dielectric layer as an implant mask; removing said second dielectric layer and said first dielectric layer; forming a gate oxide layer; forming a first conductive layer over said gate oxide layer; forming first gate-structure over said first conductivity-well region and a second gate-structure over said second conductivity-well region using a third photoresist-mask as an etching mask; forming second conductivity source/drain regions in portions of said first conductivity-well region using a fourth photoresist-mask covering said second conductivity-well region as an implant mask; forming a fourth dielectric layer over first conductivity-well region; removing said fourth photoresist-mask while leaving said fourth dielectric layer intact; forming first conductivity source/drain regions in portions of said second conductivity-well region using said fourth dielectric layer as an implant mask; forming a fifth dielectric layer over said second conductivity-well region, wherein said first and second conductivity-well regions are fully covered; forming a sixth dielectric layer over said fourth and fifth dielectric layers forming contact holes through said fourth, fifth and sixth dielectric layers using a fifth photoresist-mask as an etching mask; forming a third conductive layer on said sixth dielectric layer and in said contact holes; and forming contacts from said third conductive layer using a sixth photoresist-mask as an etching mask.

Claim 33

A method for fabricating a complementary metal-oxide-semiconductor CMOS device with no more than six photoresist-masks, the method comprising: forming field oxide regions in a substrate using a first photoresist-mask to define said field oxide regions; forming a first dielectric layer over said substrate; forming a first conductivity-well region in a portion of said substrate using a second photoresist-mask as an implant mask; forming a second dielectric layer over said first conductivity-well region, said second dielectric layer including no photoresist material; removing said second photoresist-mask while leaving said second dielectric layer intact; forming a second conductivity-well region in a portion of said substrate using said second dielectric layer as an implant mask; removing said second dielectric layer and said first dielectric layer; forming a gate oxide layer; forming a first conductive layer over said gate oxide layer; forming first gate-structure over said first conductivity-well region and a second gate-structure over said second conductivity-well region using a third photoresist-mask as an etching mask; forming second conductivity source/drain regions in portions of said first conductivity-well region using a fourth photoresist-mask covering said second conductivity-well region as an implant mask; forming a fourth dielectric layer over first conductivity-well region; removing said fourth photoresist-mask while leaving said fourth dielectric layer intact; forming first conductivity source/drain regions in portions of said second conductivity-well region using said fourth dielectric layer as an implant mask; forming a fifth dielectric layer over said second conductivity-well region, wherein said first and second conductivity-well regions are fully covered; forming a sixth dielectric layer over said fourth and fifth dielectric layers forming contact holes through said fourth, fifth and sixth dielectric layers using a fifth photoresist-mask as an etching mask; forming a third conductive layer on said sixth dielectric layer and in said contact holes; and forming contacts from said third conductive layer using a sixth photoresist-mask as an etching mask.