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US5852579A
Expired / Lapsed
US
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Method and circuit for preventing and/or inhibiting contention in a system employing a random access memory
Assignee: Monterey Research LLC
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Filing: 1997-06-19
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Granted: 1998-12-22
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Expires: 2017-06-19
Abstract
Abstract A Static Random Access Memory (SRAM) comprises an input/output pin and driver means connected to the input/output pin. The driver means are configured to drive the input/output pin to a voltage potential using a first current, and are further configured to hold the input/output pin at approximately the voltage potential using a second current. In one embodiment, the driver means may comprise a driver unit for driving the input/output pin to the voltage potential, a bus hold circuit for holding the input/output pin at the voltage potential and a control unit connected to the driver unit and the bus hold circuit. The control unit may activate and deactivate the driver unit and the bus hold circuit.
Inventors
- 👤 Mathew R. Arcoleo
- 👤 Raymond M. Leong
- 👤 Derek Johnson
- 👤 Jonathan F. Churchill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:08
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00315; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419; G11C7/00; G11C7/10; G11C7/1051; G11C7/1078
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
67 words
A Static Random Access Memory (SRAM) comprising: an input/output pin; and driver means coupled to the input/output pin and configured to drive the input/output pin to a voltage potential using a first current, and further configured to (a) hold the input/output pin at approximately the voltage potential using a second current and (b) deactivate the first current after the input/output pin is at approximately the voltage potential.
Claim 2
Dependent Claim
67 words
A Static Random Access Memory (SRAM) comprising: an input/output pin; and driver means coupled to the input/output pin and configured to drive the input/output pin to a voltage potential using a first current, and further configured to (a) hold the input/output pin at approximately the voltage potential using a second current and (b) deactivate the first current after the input/output pin is at approximately the voltage potential.
Claim 3
Dependent Claim
66 words
The SRAM of claim 1 wherein the driver means further comprises: a driver unit for driving the input/output pin to the voltage potential; a bus hold circuit for holding the input/output pin at approximately the voltage potential; and a control unit coupled to the driver unit and the bus hold circuit, the control unit for activating and deactivating the driver unit and the bus hold circuit.
Claim 4
Dependent Claim
44 words
The SRAM of claim 2 wherein the driver means uses the first current when the control unit activates the driver unit, and wherein the driver means uses the second current when the bus hold circuit holds the input/output pin at approximately the voltage potential.
Claim 5
Dependent Claim
49 words
The SRAM of claim 2 wherein the driver means uses the first current when the control unit activates the driver unit and the bus hold circuit, and wherein the driver means uses the second current when the bus hold circuit holds the input/output pin at approximately the voltage potential.
Claim 6
Dependent Claim
41 words
The SRAM of claim 2 wherein the driver unit further comprises a first pair of series-coupled transistors, each of the pair of series-coupled transistors having an input coupled to the control unit and having an output coupled to the input/output pin.
Claim 7
Dependent Claim
34 words
The SRAM of claim 5 wherein the bus hold circuit further comprises a second pair of series-coupled transistors having an input coupled to the control unit and an output coupled to the input/output pin.
Claim 8
Dependent Claim
67 words
The SRAM of claim 6 wherein the driver means further comprises a feedback circuit coupled between the driver means and the input/output pin and further coupled to the control unit, the feedback circuit configured to transmit a signal to the control unit once the input/output pin has reached the voltage potential, wherein the control unit deactivates the driver unit upon receiving the signal from the feedback circuit.
Claim 9
Dependent Claim
43 words
The output driver of claim 2 wherein the control unit comprises a timer configured to deactivate the driver unit after a predetermined time interval, wherein the predetermined time interval corresponds to a time needed to drive the input/output pin to the voltage potential.
Claim 10
Dependent Claim
63 words
An output driver circuit comprising: a driver unit for driving an input/output pin to a voltage potential using a first current; a bus hold circuit for holding the input/output pin at approximately the voltage potential using a second current; and control means coupled to the driver unit and the bus hold circuit for deactivating the driver unit after activating the bus hold circuit.
Claim 11
Dependent Claim
63 words
An output driver circuit comprising: a driver unit for driving an input/output pin to a voltage potential using a first current; a bus hold circuit for holding the input/output pin at approximately the voltage potential using a second current; and control means coupled to the driver unit and the bus hold circuit for deactivating the driver unit after activating the bus hold circuit.
Claim 12
Dependent Claim
42 words
The output driver of claim 9 wherein the driver unit further comprises a first pair of series-coupled transistors, each of the pair of series-coupled transistors having an input coupled to the control means and having an output coupled to the input/output pin.
Claim 13
Dependent Claim
35 words
The output driver of claim 10 wherein the bus hold circuit further comprises a second pair of series-coupled transistors having an input coupled to the control unit and an output coupled to the input/output pin.
Claim 14
Dependent Claim
26 words
The output driver of claim 11 wherein the control means comprise a logic circuit configured to deactivate the driver unit in response to a control signal.
Claim 15
Dependent Claim
16 words
The output driver of claim 12 wherein the control signal is received from a pin connection.
Claim 16
Independent Claim
63 words
A method of limiting bus contention comprising the steps of: driving a bus to a voltage potential using a first current provided by a driver unit; holding the bus at approximately the voltage potential using a second current provided by a bus hold circuit after the bus has reached the voltage potential; and deactivating the driver unit after activating the bus hold circuit.
Claim 17
Independent Claim
63 words
A method of limiting bus contention comprising the steps of: driving a bus to a voltage potential using a first current provided by a driver unit; holding the bus at approximately the voltage potential using a second current provided by a bus hold circuit after the bus has reached the voltage potential; and deactivating the driver unit after activating the bus hold circuit.
Claim 18
Dependent Claim
26 words
The method of claim 14 wherein the bus is driven to the voltage potential and held at approximately the voltage potential with a driver logic block.
Claim 19
Dependent Claim
22 words
The method of claim 15 wherein the driver logic block comprises: the driver unit; the bus hold circuit; and a control unit.
Claim 20
Dependent Claim
34 words
The method of claim 16 wherein the step of driving the bus to the voltage potential using a first current further comprises the step of activating the driver unit and the bus hold circuit.
Claim 21
Dependent Claim
25 words
The method of claim 17 wherein the step of deactivating the driver unit is controlled by the control unit in response to a control signal.
Claim 22
Dependent Claim
17 words
The method of claim 18 wherein the control signal is developed externally to the driver logic block.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-21 | 2002-06-22 | 2002-12-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-21 | 2006-06-22 | 2006-12-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-21 | 2010-06-22 | 2010-12-22 | $7700.00 | Window Closed / Lapsed |