Patent US5850359A successfully refreshed from Google Patents.
US5850359A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Asynchronous high speed zero DC-current SRAM system
Assignee: Philips Semiconductors Inc
•
Filing: 1996-10-29
•
Granted: 1998-12-15
•
Expires: 2016-10-29
Abstract
Abstract Bit lines coupled to a column of SRAM core cells in an array are sensed asynchronously using zero DC power with either differential sense amplifiers or single-ended amplifiers, according to the present invention. The differential sense amplifier embodiment includes a pair of cross-coupled series-connected PMOS and NMOS transistors connected between the power supplies. Each bit line is coupled to an NMOS gate in the transistor pair, and each PMOS gate is coupled to the drain-source connection of the other series-connected PMOS-NMOS pair. The PMOS gates and PMOS-NMOS drain-source connections define the sense amplifier complementary output signals, whose states are determined by the bit line states. The single-ended embodiment is implemented as a PMOS-NMOS transistor pair inverter connected between the power supplies. Each inverter input is coupled to a bit line, and the inverter outputs are the sense amplifier outputs. In both embodiments, series-connected PMOS-NMOS pairs do not provide any DC path and function asynchronously without clock or enabling signals other than the bit line signals. In either embodiment, a zero DC power consumption bit-line clamp implemented as a PMOS-NMOS inverter is also coupled to each bit line, and is controlled by the associated sense amplifier output signal. The bit-line clamp forces an associated bit line to a full "1" or "0" logic state.
Inventors
- 👤 Pin-Wu Liu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 09:53
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/065; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
98 words
A method of asychronously sensing the state stored in a core cell coupled between a bit line and a complementary bit line in a column in a memory array, the method comprising the following steps: (a) providing a first inverter having an input node coupled to said bit line and having an output node that outputs a complement of said state stored in said core cell; and (b) clamping a signal at said output node of said first inverter unit to a binary logic state; wherein said first inverter unit operates asynchronously and consumes substantially zero DC power.
Claim 2
Independent Claim
98 words
A method of asychronously sensing the state stored in a core cell coupled between a bit line and a complementary bit line in a column in a memory array, the method comprising the following steps: (a) providing a first inverter having an input node coupled to said bit line and having an output node that outputs a complement of said state stored in said core cell; and (b) clamping a signal at said output node of said first inverter unit to a binary logic state; wherein said first inverter unit operates asynchronously and consumes substantially zero DC power.
Claim 3
Dependent Claim
40 words
The method of claim 1, wherein: step (b) includes providing a second inverter having an input node coupled to said output node of said first inverter, and having an output node coupled to said input node of said first inverter.
Claim 4
Dependent Claim
20 words
The method of claim 1, wherein: said memory array includes an array of static random access memory (SRAM) core cells.
Claim 5
Dependent Claim
26 words
The method of claim 1, wherein: step (a) includes providing said first inverter unit implemented with a PMOS transistor coupled in series with an NMOS transistor.
Claim 6
Dependent Claim
17 words
The method of claim 1, wherein said first inverter unit consumes less than about 1 nA DC.
Claim 7
Dependent Claim
150 words
An asynchronously operable substantially zero DC power consuming single-ended sense amplifier useable with a system that includes an array of addressable memory core cells that are coupled between a bit line and a complementary bit line in a column in said memory array, comprising: a first inverter unit having an input node coupled to said bit line, and having an output node that outputs a signal representing a complement of a logic state stored in an addressed one of said core cells; and a second inverter unit having an input node coupled to said output node of said first inverter, and having an output node coupled to said input node of said first inverter, said second inverter clamping a signal at said output node of said first inverter unit to a binary logic state; wherein said first and said second inverter unit operate asynchronously and consume substantially zero DC power.
Claim 8
Dependent Claim
150 words
An asynchronously operable substantially zero DC power consuming single-ended sense amplifier useable with a system that includes an array of addressable memory core cells that are coupled between a bit line and a complementary bit line in a column in said memory array, comprising: a first inverter unit having an input node coupled to said bit line, and having an output node that outputs a signal representing a complement of a logic state stored in an addressed one of said core cells; and a second inverter unit having an input node coupled to said output node of said first inverter, and having an output node coupled to said input node of said first inverter, said second inverter clamping a signal at said output node of said first inverter unit to a binary logic state; wherein said first and said second inverter unit operate asynchronously and consume substantially zero DC power.
Claim 9
Dependent Claim
31 words
The sense amplifier of claim 6, wherein at least one of said first inverter unit and said second inverter unit comprises a PMOS transistor coupled in series with an NMOS transistor.
Claim 10
Dependent Claim
21 words
The sense amplifier of claim 6, wherein: said memory array includes an array of static random access memory (SRAM) core cells.
Claim 11
Dependent Claim
125 words
The sense amplifier of claim 6, further including a second asynchronously operable substantially zero DC power consuming single-ended sense amplifier comprising: a third inverter unit having an input node coupled to said complementary bit line, and having an output node that outputs a signal representing said logic state stored in an addressed one of said core cells; and a fourth inverter unit having an input node coupled to said output node of said third inverter, and having an output node coupled to said input node of said third inverter, said fourth inverter clamping a signal at said output node of said first inverter unit to a binary logic state; wherein said third and said fourth inverter unit operate asynchronously and consume substantially zero DC power.
Claim 12
Dependent Claim
17 words
The sense amplifier of claim 6, wherein said sense amplifier consumes less than about 1 nA DC.
Claim 13
Dependent Claim
152 words
An integrated circuit comprising: an array of addressable static random access memory core cells including core cells coupled to a bit line and a complementary bit line in a column in said array; and an asynchronously operable substantially zero DC power consuming single-ended sense amplifier comprising: a first inverter unit having an input node coupled to said bit line, and having an output node that outputs a signal representing a complement of a logic state stored in an addressed one of said core cells; and a second inverter unit having an input node coupled to said output node of said first inverter, and having an output node coupled to said input node of said first inverter, said second inverter clamping a signal at said output node of said first inverter unit to a binary logic state; wherein said first and said second inverter unit operate asynchronously and consume substantially zero DC power.
Claim 14
Dependent Claim
152 words
An integrated circuit comprising: an array of addressable static random access memory core cells including core cells coupled to a bit line and a complementary bit line in a column in said array; and an asynchronously operable substantially zero DC power consuming single-ended sense amplifier comprising: a first inverter unit having an input node coupled to said bit line, and having an output node that outputs a signal representing a complement of a logic state stored in an addressed one of said core cells; and a second inverter unit having an input node coupled to said output node of said first inverter, and having an output node coupled to said input node of said first inverter, said second inverter clamping a signal at said output node of said first inverter unit to a binary logic state; wherein said first and said second inverter unit operate asynchronously and consume substantially zero DC power.
Claim 15
Dependent Claim
31 words
The integrated circuit of claim 11, wherein at least one of said first inverter unit and said second inverter unit comprises a PMOS transistor coupled in series with an NMOS transistor.
Claim 16
Dependent Claim
125 words
The integrated circuit of claim 11, further including: a second asynchronously operable substantially zero DC power consuming single-ended sense amplifier comprising: a third inverter unit having an input node coupled to said complementary bit line, and having an output node that outputs a signal representing said logic state stored in an addressed one of said core cells; and a fourth inverter unit having an input node coupled to said output node of said third inverter, and having an output node coupled to said input node of said third inverter, said fourth inverter clamping a signal at said output node of said first inverter unit to a binary logic state; wherein said third and said fourth inverter unit operate asynchronously and consume substantially zero DC power.
Claim 17
Dependent Claim
17 words
The integrated circuit of claim 11, wherein said sense amplifier consumes less than about 1 nA DC.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-14 | 2002-06-15 | 2002-12-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-14 | 2006-06-15 | 2006-12-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-14 | 2010-06-15 | 2010-12-15 | $7700.00 | Window Closed / Lapsed |