US5034923A
Expired / Lapsed
US
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Static RAM with soft defect detection
Assignee: NXP USA Inc
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Filing: 1988-12-05
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Granted: 1991-07-23
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Expires: 2008-12-05
Abstract
Abstract A static RAM includes test features which provide for the detection of soft defects which may cause a defective SRAM cell to behave as a functional DRAM cell. Provision is made for writing either a high or a low logic state to each bit line of the SRAM while not writing any value to its complementary bit line and for sensing the state of each bit line independently of the state of its complementary bit line. In addition, a current test is provided which detects soft defects by means of the increased inverter leakage current caused thereby. It is possible, by properly combining these tests, to reliably detect all soft defects, thereby assuring the data retention capability of the SRAM. This technique avoids the long hold time and/or high temperature test techniques used in the prior art.
Inventors
- 👤 Clinton C. K. Kuo
- 👤 Ernest A. Carter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:15
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/02; G11C29/025; G11C29/04; G11C29/50; G11C29/50016; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C2029/5006
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
116 words
A memory device comprising: a memory cell; a word line; a pair of complementary bit lines selectably coupled to said memory cell under control of said word line; input logic means for simultaneously controlling a state of both said complementary bit lines during a normal write mode and for controlling a state of one of said complementary bit lines while leaving a state of the other of said complementary bit lines uncontrolled during a soft defect detection mode; and sensing means for simultaneously controlling a state of both said complementary bit lines during a normal write mode and for sensing the state of said other of said complementary bit lines during the soft defect detection mode.
Claim 2
Dependent Claim
116 words
A memory device comprising: a memory cell; a word line; a pair of complementary bit lines selectably coupled to said memory cell under control of said word line; input logic means for simultaneously controlling a state of both said complementary bit lines during a normal write mode and for controlling a state of one of said complementary bit lines while leaving a state of the other of said complementary bit lines uncontrolled during a soft defect detection mode; and sensing means for simultaneously controlling a state of both said complementary bit lines during a normal write mode and for sensing the state of said other of said complementary bit lines during the soft defect detection mode.
Claim 3
Dependent Claim
20 words
A memory device according to claim 1 further comprising: means for sensing a leakage current flowing through said memory cell.
Claim 4
Dependent Claim
33 words
A memory device according to claim 1 further comprising: means for precharging said bit lines, said means for precharging being capable of precharging said bit lines to both high state and low states.
Claim 5
Dependent Claim
77 words
A memory device according to claim 1 further comprising: a Y-select line; a pair of complementary data lines selectably coupled to said pair of complementary bit lines under control of said Y-select line; and wherein said input logic means further comprises: means for simultaneously controlling a state of both said complementary data lines during the normal write mode and for controlling the state of only one of said complementary data lines during the soft defect detection mode.
Claim 6
Dependent Claim
52 words
A memory device according to claim 4 wherein said sensing means further comprises: a differential sense amplifier coupled to both said complementary data lines; a first non-differential sense amplifier coupled to one of said complementary data lines; and a second non-differential sense amplifier coupled to the other of said complementary data lines.
Claim 7
Dependent Claim
212 words
A memory device comprising: an array comprising a plurality of memory cells; a plurality of word lines intersecting said array; a plurality of complementary bit line pairs intersecting said array, each of said memory cells being couple-able to one of said complementary bit line pairs under control of one of said word lines; a complementary data line pair; a plurality of Y-select lines, said complementary data line pair being couple-able to at least one of said complementary bit line pairs under control of one of said plurality of Y-select lines; control means; input means couple-able to said complementary data line pair for simultaneously controlling a state of both said complementary data lines during a normal write mode and for controlling the state of only one of said complementary data lines during a soft defect detection mode, said input means being under control of said control means to determine the mode of said input means; and sense amplifier means for simultaneously sensing the states of said complementary data lines during a normal read mode and for sensing the state of only one of said complementary data lines during a soft defect detection mode, said sense amplifier means being under control of said control means to determine the mode of said sense amplifier means.
Claim 8
Dependent Claim
212 words
A memory device comprising: an array comprising a plurality of memory cells; a plurality of word lines intersecting said array; a plurality of complementary bit line pairs intersecting said array, each of said memory cells being couple-able to one of said complementary bit line pairs under control of one of said word lines; a complementary data line pair; a plurality of Y-select lines, said complementary data line pair being couple-able to at least one of said complementary bit line pairs under control of one of said plurality of Y-select lines; control means; input means couple-able to said complementary data line pair for simultaneously controlling a state of both said complementary data lines during a normal write mode and for controlling the state of only one of said complementary data lines during a soft defect detection mode, said input means being under control of said control means to determine the mode of said input means; and sense amplifier means for simultaneously sensing the states of said complementary data lines during a normal read mode and for sensing the state of only one of said complementary data lines during a soft defect detection mode, said sense amplifier means being under control of said control means to determine the mode of said sense amplifier means.
Claim 9
Dependent Claim
27 words
A memory device according to claim 6 further comprising: current sense means coupled to each of said plurality of memory cells for sensing a leakage current therethrough.
Claim 10
Dependent Claim
29 words
A memory device according to claim 6 wherein: said current sense means is under control of said control means to sense said leakage current during a current sense mode.
Claim 11
Dependent Claim
72 words
A memory device according to claim 6 further comprising: first precharge means for precharging each of said complementary bit lines to one of a high and a low state, said first precharge means being under control of said control means; and second precharge means for precharging each of said complementary data lines to one of a high and a low state, said second precharge means being under control of said control means.
Claim 12
Dependent Claim
53 words
A memory device according to claim 9 wherein: said control means is responsive to a state of said input means, during a soft defect detection mode, to direct said first and second precharge means to precharge said bit lines and data lines to a state identical to said state of said input means.
Claim 13
Dependent Claim
244 words
An integrated circuit microcomputer comprising: a central processing unit; a memory unit; and communication means coupled to the central processing unit and to the memory unit for providing communication therebetween; wherein the memory unit further comprises: an array comprising a plurality of memory cells; a plurality of word lines intersecting said array; a plurality of complementary bit line pairs intersecting said array, each of said memory cells being couple-able to one of said complementary bit line pairs under control of one of said word lines; a complementary data line pair; a plurality of Y-select lines, said complementary data line pair being couple-able to at least one of said complementary bit line pairs under control of one of said plurality of Y-select lines; control means; input means couple-able to said complementary data line pair for simultaneously controlling a state of both said complementary data lines during a normal write mode and for controlling the state of only one of said complementary data lines during a soft defect detection mode, said input means being under control of said control means to determine the mode of said input means; and sense amplifier means for simultaneously sensing the states of said complementary data lines during a normal read mode and for sensing the state of only one of said complementary data lines during a soft defect detection mode, said sense amplifier means being under control of said control means to determine the mode of said sense amplifier means.
Claim 14
Dependent Claim
244 words
An integrated circuit microcomputer comprising: a central processing unit; a memory unit; and communication means coupled to the central processing unit and to the memory unit for providing communication therebetween; wherein the memory unit further comprises: an array comprising a plurality of memory cells; a plurality of word lines intersecting said array; a plurality of complementary bit line pairs intersecting said array, each of said memory cells being couple-able to one of said complementary bit line pairs under control of one of said word lines; a complementary data line pair; a plurality of Y-select lines, said complementary data line pair being couple-able to at least one of said complementary bit line pairs under control of one of said plurality of Y-select lines; control means; input means couple-able to said complementary data line pair for simultaneously controlling a state of both said complementary data lines during a normal write mode and for controlling the state of only one of said complementary data lines during a soft defect detection mode, said input means being under control of said control means to determine the mode of said input means; and sense amplifier means for simultaneously sensing the states of said complementary data lines during a normal read mode and for sensing the state of only one of said complementary data lines during a soft defect detection mode, said sense amplifier means being under control of said control means to determine the mode of said sense amplifier means.
Claim 15
Dependent Claim
28 words
An integrated circuit microcomputer according to claim 11 further comprising: current sense means coupled to each of said plurality of memory cells for sensing a leakage current therethrough.
Claim 16
Dependent Claim
30 words
An integrated circuit microcomputer according to claim 12 wherein: said current sense means is under control of said control means to sense said leakage current during a current sense mode.
Claim 17
Dependent Claim
73 words
An integrated circuit microcomputer according to claim 11 further comprising: first precharge means for precharging each of said complementary bit lines to one of a high and a low state, said first precharge means being under control of said control means; and second precharge means for precharging each of said complementary data lines to one of a high and a low state, said second precharge means being under control of said control means.
Claim 18
Dependent Claim
54 words
An integrated circuit microcomputer according to claim 14 wherein: said control means is responsive to a state of said input means, during a soft defect detection mode, to direct said first and second precharge means to precharge said bit lines and data lines to a state identical to said state of said input means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-22 | 1995-01-21 | 1995-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-22 | 1999-01-21 | 1999-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-22 | 2003-01-21 | 2003-07-23 | $7700.00 | Window Closed / Lapsed |