Patent US5848247A successfully refreshed from Google Patents.
US5848247A
Expired / Lapsed
US
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Microprocessor having PC card interface
Assignee: Renesas Electronics Corp
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Filing: 1995-09-07
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Granted: 1998-12-08
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Expires: 2015-09-07
Abstract
Abstract A microprocessor comprising a bus state controller and for use in a personal computer or the like. The bus state controller includes control registers such as wait controllers, and in parallel controls the interfaces of various semiconductor memories (ROM, burst ROM, SRAM, PSRAM, DRAM and synchronous RAM) and PC cards (memory and I/O cards). Also included in the bus state controller is a control register for controlling the time to set up PC card start signals where a synchronous DRAM(s) is configured. The address space of an external bus of the microprocessor is divided into a predetermined number of areas to which the semiconductor memories and PC cards are fixedly assigned. The microprocessor further comprises a memory management unit for converting an internally prepared logical address to a physical address.
Inventors
- 👤 Shigezumi Matsui
- 👤 Ikuya Kawasaki
- 👤 Susumu Narita
- 👤 Masato Nemoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:08
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F12/00; G06F12/02; G06F12/06; G06F13/382; G06F13/385; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243; G06F12/0223; G06F12/0292
Claims Analysis
Total Claims: 49
Claim 1
Independent Claim
159 words
A microprocessor formed on a semiconductor substrate comprising an interface circuit, wherein the interface circuit provides an interface for connecting semiconductor memories and one or more PC cards directly to the microprocessor; wherein the interface circuit generates a plurality of control signals to control an external bus coupled to the microprocessor; wherein the semiconductor memories include a ROM, a burst ROM, an SRAM, a PSRAM, a DRAM and/or a synchronous DRAM; wherein the PC cards comprise a memory card and/or an I/O card; wherein the microprocessor accesses the external bus using physical addresses in an address space, wherein the address space is divided into a plurality of areas assigned fixedly to predetermined semiconductor memories and PC cards, and wherein the microprocessor further comprises a central processing unit that outputs an internal logical address and a memory management unit coupled to the central processing unit that converts the internal logical address to a physical address applicable to the external bus.
Claim 2
Dependent Claim
159 words
A microprocessor formed on a semiconductor substrate comprising an interface circuit, wherein the interface circuit provides an interface for connecting semiconductor memories and one or more PC cards directly to the microprocessor; wherein the interface circuit generates a plurality of control signals to control an external bus coupled to the microprocessor; wherein the semiconductor memories include a ROM, a burst ROM, an SRAM, a PSRAM, a DRAM and/or a synchronous DRAM; wherein the PC cards comprise a memory card and/or an I/O card; wherein the microprocessor accesses the external bus using physical addresses in an address space, wherein the address space is divided into a plurality of areas assigned fixedly to predetermined semiconductor memories and PC cards, and wherein the microprocessor further comprises a central processing unit that outputs an internal logical address and a memory management unit coupled to the central processing unit that converts the internal logical address to a physical address applicable to the external bus.
Claim 3
Dependent Claim
34 words
A microprocessor according to claim 1, wherein the external bus is capable of having at least part of the semiconductor memories connected concurrently with the memory card and/or the I/O card to the microprocessor.
Claim 4
Dependent Claim
50 words
A microprocessor according to claim 2, wherein the I/O card functions either as an I/O device or a memory, and wherein the physical addresses applicable when the I/O card acts as the I/O device are assigned independently of the physical addresses applicable when the I/O card functions as the memory.
Claim 5
Dependent Claim
50 words
A microprocessor according to claim 1, further comprising: a bus state controller including registers for interface control between the semiconductor memories and the microprocessor and/or between the PC cards and the microprocessor, wherein the registers set operating conditions of the semiconductor memories and/or the PC cards assigned to the areas.
Claim 6
Dependent Claim
47 words
A microprocessor according to claim 4, wherein at least part of the semiconductor memories and the PC cards have a burst mode for consecutive access to a series of addresses, and wherein the bus state controller has an address generating circuit for use in the burst mode.
Claim 7
Dependent Claim
15 words
A microprocessor according to claim 5, wherein the bus state controller comprises a state machine.
Claim 8
Dependent Claim
69 words
A microprocessor formed on a semiconductor substrate comprising: a central processing unit capable of accessing an external address space of the microprocessor, the external address space being divided into a plurality of areas; and a controller which generates control signals for accessing the external address space, wherein the controller includes a register which stores data defining that one of the plurality of areas is assigned to a PC card.
Claim 9
Dependent Claim
69 words
A microprocessor formed on a semiconductor substrate comprising: a central processing unit capable of accessing an external address space of the microprocessor, the external address space being divided into a plurality of areas; and a controller which generates control signals for accessing the external address space, wherein the controller includes a register which stores data defining that one of the plurality of areas is assigned to a PC card.
Claim 10
Dependent Claim
36 words
A microprocessor according to claim 7, wherein the controller is capable of providing a card enable signal as one of the control signals in response to an access to the card from the central processing unit.
Claim 11
Dependent Claim
44 words
A microprocessor according to claim 7, wherein the controller selectively provides an output enable signal, a write enable signal, an I/O read control signal and an I/O write control signal for the card to control access to the card by the central processing unit.
Claim 12
Dependent Claim
14 words
A microprocessor according to claim 7, wherein the PC card comprises a PCMCIA card.
Claim 13
Dependent Claim
69 words
A microprocessor formed on a semiconductor substrate comprising: a central processing unit capable of accessing an external address space of the microprocessor by generating address signals; and an interface circuit which generates control signals for accessing a PC card, wherein an address space of the card is assigned in the external address space of the microprocessor, and the card is accessed by the control signals and the address signals.
Claim 14
Dependent Claim
69 words
A microprocessor formed on a semiconductor substrate comprising: a central processing unit capable of accessing an external address space of the microprocessor by generating address signals; and an interface circuit which generates control signals for accessing a PC card, wherein an address space of the card is assigned in the external address space of the microprocessor, and the card is accessed by the control signals and the address signals.
Claim 15
Dependent Claim
14 words
A microprocessor according to claim 11, wherein the PC card comprises a PCMCIA card.
Claim 16
Dependent Claim
97 words
A microprocessor formed on a semiconductor substrate comprising: a central processing unit which generates logical address signals to access an external address space of the microprocessor, wherein the external address space includes an address space for a PC card; a memory management unit which converts the logical address signals into physical address signals; a bus controller including: means for receiving the physical address signals to provide the received physical address signals external to the microprocessor; and means for generating control signals for the card in response to an access of the card by the physical address signals.
Claim 17
Dependent Claim
97 words
A microprocessor formed on a semiconductor substrate comprising: a central processing unit which generates logical address signals to access an external address space of the microprocessor, wherein the external address space includes an address space for a PC card; a memory management unit which converts the logical address signals into physical address signals; a bus controller including: means for receiving the physical address signals to provide the received physical address signals external to the microprocessor; and means for generating control signals for the card in response to an access of the card by the physical address signals.
Claim 18
Dependent Claim
22 words
A microprocessor according to claim 13, wherein an address area assigned to the card is fixedly allocated in the external address space.
Claim 19
Dependent Claim
23 words
A microprocessor according to claim 13, wherein the control signals include a card enable signal for enabling the microprocessor to access the card.
Claim 20
Dependent Claim
50 words
A microprocessor according to claim 15, wherein the card includes a memory card or an I/O card, and wherein the control signals include an output enable signal and a write enable signal for the memory card or a read control signal and a write control signal for the I/O card.
Claim 21
Dependent Claim
14 words
A microprocessor according to claim 13, wherein the PC card comprises a PCMCIA card.
Claim 22
Dependent Claim
182 words
A bus state controller in an integrated microprocessor, comprising: address providing means for providing an address signal in response to an access to an external address space which is divided into a plurality of address areas; data means for providing and receiving data to and from an address of one of the plurality of address areas which is accessed by the address signal; first register means for storing attribute data that defines attributes of the plurality of address areas, wherein one of the plurality of address areas is assigned for a PC card; control signal generating means coupled to the first register means and for providing control signals including a card enable signal which enables the card in response to an access to the card by the address signal; second register means for storing first data which defines a delay time to set up the address signal for start control signals for the card; and timing control means coupled to the second register and for generating the start control signals in accordance with the first data stored in the second register means.
Claim 23
Dependent Claim
182 words
A bus state controller in an integrated microprocessor, comprising: address providing means for providing an address signal in response to an access to an external address space which is divided into a plurality of address areas; data means for providing and receiving data to and from an address of one of the plurality of address areas which is accessed by the address signal; first register means for storing attribute data that defines attributes of the plurality of address areas, wherein one of the plurality of address areas is assigned for a PC card; control signal generating means coupled to the first register means and for providing control signals including a card enable signal which enables the card in response to an access to the card by the address signal; second register means for storing first data which defines a delay time to set up the address signal for start control signals for the card; and timing control means coupled to the second register and for generating the start control signals in accordance with the first data stored in the second register means.
Claim 24
Dependent Claim
60 words
A bus state controller according to claim 18, wherein the second register means further stores second data which defines a delay time of an address hold time to hold the address signal for start control signals, and wherein the timing control means is responsive to the second data and controls the address hold time in accordance with the second data.
Claim 25
Dependent Claim
53 words
A bus state controller according to claim 18, wherein the address providing means further includes an address generation circuit which updates automatically certain bits of the address signal in burst mode in which a series of addresses are accessed consecutively, wherein the address generation circuit generates address signals sequentially in the burst mode.
Claim 26
Dependent Claim
53 words
A bus state controller according to claim 18, wherein the card includes a memory card or an I/O card, and wherein the start control signals include an output enable signal and a write enable signal for the memory card, or a read control signal and a write control signal for the I/O card.
Claim 27
Dependent Claim
24 words
A bus state controller according to claim 18, wherein the address area assigned to the card is fixedly allocated in the external address space.
Claim 28
Dependent Claim
16 words
A bus state controller according to claim 18, wherein the PC card comprises a PCMCIA card.
Claim 29
Dependent Claim
80 words
A microprocessor on a semiconductor substrate comprising: a central processing unit that provides an address signal to access an address in an external address space of the microprocessor, wherein the external address space includes an address space for a PC card; a controller that is responsive to an access of the external address space and provides card enable signals to enable the microprocessor to access the PC card when the address is in the address space for the PC card.
Claim 30
Dependent Claim
80 words
A microprocessor on a semiconductor substrate comprising: a central processing unit that provides an address signal to access an address in an external address space of the microprocessor, wherein the external address space includes an address space for a PC card; a controller that is responsive to an access of the external address space and provides card enable signals to enable the microprocessor to access the PC card when the address is in the address space for the PC card.
Claim 31
Dependent Claim
33 words
A microprocessor according to claim 24, wherein the controller includes a register that stores data representing where the address space for the PC card is within the external address space of the microprocessor.
Claim 32
Dependent Claim
43 words
A microprocessor according to claim 25, wherein the PC card includes an I/O card and/or a memory card, and wherein an address space of the I/O card is allocated within the external address space independently of an address space of the memory card.
Claim 33
Dependent Claim
105 words
A microprocessor according to claim 24, further comprising: a memory management unit which converts the address signal as an internal logical address signal generated from the central processing unit to an external address signal as a physical address signal applicable to an external bus that is to be coupled to the microprocessor, wherein the external address space of the microprocessor is divided into a plurality of address spaces, and wherein the controller includes a register that stores data representing that the address space for the PC card is allocated to one of the plurality of address spaces in the external address space of the microprocessor.
Claim 34
Dependent Claim
62 words
A microprocessor according to claim 27, wherein the controller further includes: an address providing circuit coupled to receive the physical address signal and providing the received physical address signal external to the microprocessor; and a control signal providing circuit responsive to an access of the address space for the PC card and for providing the card enable signals external to the microprocessor.
Claim 35
Dependent Claim
62 words
A microprocessor according to claim 28, wherein the PC card includes an I/O card and/or a memory card, wherein the I/O card functions either as an I/O device or a memory, and wherein the physical addresses applicable when the I/O card acts as the I/O device are allocated independently of the physical address applicable when the I/O card functions as the memory.
Claim 36
Dependent Claim
14 words
A microprocessor according to claim 24, wherein the PC card comprises a PCMCIA card.
Claim 37
Dependent Claim
156 words
A microprocessor on a semiconductor substrate comprising: a central processing unit for providing an address signal to access an address in an external address space of the microprocessor; first terminals; second terminals; an address control circuit coupled to the first terminals and for delivering the address signals from the central processing unit external to the microprocessor; a data input and output circuit coupled to the second terminals; and a control signal generation circuit responsive to the address signal and for generating control signals external to the microprocessor, wherein the control signal generation circuit provides card enable signals as the control signal when detecting that the address signal designates an address in a first address space for a card, and wherein the control signal generation circuit generates a chip select signal as the control signal for a semiconductor memory when detecting that the address signal designates an address in a second address space for the semiconductor memory.
Claim 38
Dependent Claim
156 words
A microprocessor on a semiconductor substrate comprising: a central processing unit for providing an address signal to access an address in an external address space of the microprocessor; first terminals; second terminals; an address control circuit coupled to the first terminals and for delivering the address signals from the central processing unit external to the microprocessor; a data input and output circuit coupled to the second terminals; and a control signal generation circuit responsive to the address signal and for generating control signals external to the microprocessor, wherein the control signal generation circuit provides card enable signals as the control signal when detecting that the address signal designates an address in a first address space for a card, and wherein the control signal generation circuit generates a chip select signal as the control signal for a semiconductor memory when detecting that the address signal designates an address in a second address space for the semiconductor memory.
Claim 39
Dependent Claim
65 words
A microprocessor according to claim 31, wherein the external address space of the microprocessor is divided into a plurality of address spaces which include the first and second address spaces, wherein the control signal generation circuit includes a register which stores data defining that the first address space is allocated to the card and that the second address space is allocated to the semiconductor memory.
Claim 40
Dependent Claim
43 words
A microprocessor according to claim 31, wherein the address control circuit includes an address generating circuit for automatically updating a bit of the address signal in a burst mode in which a series of addresses in the external address space is accessed consecutively.
Claim 41
Dependent Claim
55 words
A microprocessor according to claim 31, further comprising: a memory management unit which converts the address signals as a logical address signal generated from the central processing unit into a physical address signal, wherein the address control circuit receives the physical address signal as the address signal and provides address signals to the first terminals.
Claim 42
Dependent Claim
182 words
A microprocessor formed on a semiconductor substrate comprising an interface circuit, wherein the interface circuit provides an interface for connecting semiconductor memories and one or more PC cards directly to the microprocessor; wherein the interface circuit generates a plurality of control signals to control the semiconductor memories and the PC cards, wherein the semiconductor memories and the PC cards are coupled to the microprocessor via an external bus which is coupled to the microprocessor; wherein the semiconductor memories include a ROM, a burst ROM, an SRAM, a PSRAM, a DRAM and/or a synchronous DRAM; wherein the PC cards comprise a memory card and/or an I/O card; wherein the microprocessor accesses the external bus using physical addresses in an address space, wherein the address space is divided into a plurality of areas assigned fixedly to predetermined semiconductor memories and PC cards, and wherein the microprocessor further comprises a central processing unit that outputs an internal logical address and a memory management unit coupled to the central processing unit that converts the internal logical address to a physical address applicable to the external bus.
Claim 43
Dependent Claim
182 words
A microprocessor formed on a semiconductor substrate comprising an interface circuit, wherein the interface circuit provides an interface for connecting semiconductor memories and one or more PC cards directly to the microprocessor; wherein the interface circuit generates a plurality of control signals to control the semiconductor memories and the PC cards, wherein the semiconductor memories and the PC cards are coupled to the microprocessor via an external bus which is coupled to the microprocessor; wherein the semiconductor memories include a ROM, a burst ROM, an SRAM, a PSRAM, a DRAM and/or a synchronous DRAM; wherein the PC cards comprise a memory card and/or an I/O card; wherein the microprocessor accesses the external bus using physical addresses in an address space, wherein the address space is divided into a plurality of areas assigned fixedly to predetermined semiconductor memories and PC cards, and wherein the microprocessor further comprises a central processing unit that outputs an internal logical address and a memory management unit coupled to the central processing unit that converts the internal logical address to a physical address applicable to the external bus.
Claim 44
Dependent Claim
34 words
A microprocessor according to claim 35, wherein the external bus is capable of having at least part of the semiconductor memories connected concurrently with the memory card and/or the I/O card to the microprocessor.
Claim 45
Dependent Claim
50 words
A microprocessor according to claim 36, wherein the I/O card functions either as an I/O device or a memory, and wherein the physical addresses applicable when the I/O card acts as the I/O device are assigned independently of thc physical addresses applicable when the I/O card functions as the memory.
Claim 46
Dependent Claim
50 words
A microprocessor according to claim 35, further comprising: a bus state controller including registers for interface control between the semiconductor memories and the microprocessor and/or between the PC cards and the microprocessor, wherein the registers set operating conditions of the semiconductor memories and/or the PC cards assigned to the areas.
Claim 47
Dependent Claim
47 words
A microprocessor according to claim 38, wherein at least part of the semiconductor memories and the PC cards have a burst mode for consecutive access to a series of addresses, and wherein the bus state controller has an address generating circuit for use in the burst mode.
Claim 48
Dependent Claim
15 words
A microprocessor according to claim 39, wherein the bus state controller comprises a state machine.
Claim 49
Dependent Claim
14 words
A microprocessor according to claim 35, wherein the PC card comprises a PCMCIA card.
References Cited (Backward Citations)
US5537654A
Cited
US5574654A
Cited
US5519851A
Cited
US5596728A
Cited
US5590373A
Cited
US5604870A
Cited
US5555510A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-07 | 2002-06-08 | 2002-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-07 | 2006-06-08 | 2006-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-07 | 2010-06-08 | 2010-12-08 | $7700.00 | Window Closed / Lapsed |