US5604870A
Expired / Lapsed
US
⏱️ 0.0 years remaining
UART emulator card
Assignee: Google Technology Holdings LLC
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Filing: 1994-08-01
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Granted: 1997-02-18
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Expires: 2014-08-01
Abstract
Abstract An interface device (102) and corresponding method for coupling a peripheral controller (117) to a host computer (100), the interface device including an emulated universal asynchronous receiver transmitter (UART) (113) for the host computer. The interface device further includes a plurality of registers (203), preferably a control (215), status (227), and data register, such as a multi-register data buffer (401), corresponding to the registers of a UART, a host computer port (112), preferably compatible with a PCMCIA standard, that includes an address map for the plurality of registers (203), a peripheral controller port (114) providing an address mapped parallel interface to the plurality of registers (203), and control logic (207) for providing status signals, including UART status signals, to the host computer port and to the peripheral controller port. The interface device may further include a pacing circuit (303) for substantially emulating, preferably dependent on a baud rate of the data information, the timing limitations of the UART.
Inventors
- 👤 Barry Moss
- 👤 Denis Beaudoin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 04:32
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/105
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
116 words
A peripheral card adapted for coupling to a host processor, comprising: an emulated universal asynchronous receiver transmitter (UART) comprising: a plurality of registers corresponding to the registers of a UART, a host processor port having a first address mapped parallel interface for said plurality of registers, a peripheral controller port having a second address mapped parallel interface for said plurality of registers, and control logic for providing status signals, including UART signals, to said host processor port and to said peripheral controller port; a peripheral card parallel interface coupled to said host processor port and adapted for coupling to a parallel interface of said host processor; a peripheral card controller coupled to the peripheral controller port.
Claim 2
Dependent Claim
116 words
A peripheral card adapted for coupling to a host processor, comprising: an emulated universal asynchronous receiver transmitter (UART) comprising: a plurality of registers corresponding to the registers of a UART, a host processor port having a first address mapped parallel interface for said plurality of registers, a peripheral controller port having a second address mapped parallel interface for said plurality of registers, and control logic for providing status signals, including UART signals, to said host processor port and to said peripheral controller port; a peripheral card parallel interface coupled to said host processor port and adapted for coupling to a parallel interface of said host processor; a peripheral card controller coupled to the peripheral controller port.
Claim 3
Dependent Claim
22 words
The peripheral card of claim 1 wherein said plurality of registers comprise a control register, a status register, and a data register.
Claim 4
Dependent Claim
17 words
The peripheral card of claim 1 wherein said plurality of registers further comprise a multi-register data buffer.
Claim 5
Dependent Claim
31 words
The peripheral card of claim 3 wherein said multi-register data buffer further includes a pacing circuit controlling the emulated UART to have timing limitations corresponding to timing limitations of said UART.
Claim 6
Dependent Claim
18 words
The peripheral card of claim 4 wherein said pacing circuit is dependent on a baud rate of data.
Claim 7
Dependent Claim
18 words
The peripheral card of claim 5 wherein said peripheral card parallel interface is compatible with a PCMCIA standard.
Claim 8
Dependent Claim
24 words
The peripheral card of claim 1 wherein said plurality of registers further includes a multi-register data buffer for transmit data and for receive data.
Claim 9
Dependent Claim
37 words
The peripheral card of claim 7 wherein said multi-register data buffer further includes a pacing circuit for emulating the timing limitations of said UART, said pacing circuit operating for said transmit data and for said receive data.
Claim 10
Dependent Claim
20 words
The peripheral card of claim 8 wherein said pacing circuit is dependent on a baud rate of said transmit data.
Claim 11
Dependent Claim
20 words
The peripheral card of claim 9 wherein said pacing circuit is dependent on a baud rate of said receive data.
Claim 12
Dependent Claim
42 words
The peripheral card of claim 1 wherein the peripheral card is a PCMCIA card, said peripheral card parallel interface is compatible with a PCMCIA standard, and the peripheral card further comprising an rf (radio frequency) modem coupled to the peripheral card controller.
Claim 13
Dependent Claim
115 words
In a peripheral card including a peripheral controller and a peripheral card parallel interface adapted for coupling to a host processor, a method comprising: providing a plurality of registers corresponding to the registers of a UART (universal asynchronous receiver transmitter) including a peripheral controller parallel port coupling the peripheral controller and the plurality of registers, and a host processor parallel port coupling the peripheral card parallel interface and the plurality registers; parallel mapping signals between the peripheral controller parallel port and said plurality of registers in a manner emulating a UART, and further parallel mapping the signals between the plurality of registers and the host processor parallel port in a manner further emulating a UART.
Claim 14
Dependent Claim
115 words
In a peripheral card including a peripheral controller and a peripheral card parallel interface adapted for coupling to a host processor, a method comprising: providing a plurality of registers corresponding to the registers of a UART (universal asynchronous receiver transmitter) including a peripheral controller parallel port coupling the peripheral controller and the plurality of registers, and a host processor parallel port coupling the peripheral card parallel interface and the plurality registers; parallel mapping signals between the peripheral controller parallel port and said plurality of registers in a manner emulating a UART, and further parallel mapping the signals between the plurality of registers and the host processor parallel port in a manner further emulating a UART.
Claim 15
Dependent Claim
29 words
The method of claim 12 further including a step of storing at least one of the group consisting of control, status, and data information in said plurality of registers.
Claim 16
Dependent Claim
32 words
The method of claim 13 further including a step of pacing said step of storing in said plurality of registers, said step of pacing comprising emulating the timing limitations of said UART.
Claim 17
Dependent Claim
20 words
The method of claim 14 wherein said step of pacing is further dependent on a baud rate of said information.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-18 | 2000-08-19 | 2001-02-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-18 | 2004-08-19 | 2005-02-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-18 | 2008-08-19 | 2009-02-18 | $7700.00 | Window Closed / Lapsed |