Row decoding circuit for semiconductor non-volatile electrically programmable memory and corresponding method

Claim 2

A row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of a type having a matrix of memory cells laid out as cell rows and columns, the matrix being divided into sectors such that each sector has a corresponding plurality of rows, the row decoding circuit comprising: an input stage that receives input row decode signals and the supply voltages; and an output stage that is driven by the input row decode signals and supply voltages, the output stage having: a complementary pair of high-voltage MOS transistors including a pull-up transistor and a pull-down transistor, wherein the pull-up and pull-down transistors are connected to form an output terminal wherein the output terminal is connected to a plurality of rows corresponding to a sector of the matrix, and a MOS transistor of the P-channel depletion type with enhanced gate oxide, wherein the MOS transistor is disposed between the output terminal and the pull-down transistor; wherein the input stage and output stage forms a row decoder coupled to the sector of the matrix, wherein the row decoding circuit further comprises a plurality of local switches, one of the local switches being associated with the row decoder and providing the supply voltages to the row decoder.

Claim 3

A row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of a type having a matrix of memory cells laid out as cell rows and columns, the matrix being divided into sectors such that each sector has a corresponding plurality of rows, the row decoding circuit comprising: an input stage that receives input row decode signals and the supply voltages; and an output stage that is driven by the input row decode signals and supply voltages, the output stage having: a complementary pair of high-voltage MOS transistors including a pull-up transistor and a pull-down transistor, wherein the pull-up and pull-down transistors are connected to form an output terminal, wherein the output terminal is connected to a plurality of rows corresponding to a sector of the matrix, and a MOS transistor of the P-channel depletion type with enhanced gate oxide, wherein the MOS transistor is disposed between the output terminal and the pull-down transistor; and a voltage generator incorporating a charge pump; and a switching device including: a main switch connected to a supply voltage reference and the voltage generator, and a set of local switches connected to the main switch, each local switch being associated with a sector of the matrix.

Claim 4

A row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of a type having a matrix of memory cells laid out as cell rows and columns, the matrix being divided into sectors such that each sector has a corresponding plurality of rows, the row decoding circuit comprising: an input stage that receives input row decode signals and the supply voltages; and an output stage that is driven by the input row decode signals and supply voltages, the output stage having: a complementary pair of high-voltage MOS transistors including a pull-up transistor and a pull-down transistor, wherein the pull-up and pull-down transistors are connected to form an output terminal, wherein the output terminal is connected to a plurality of rows corresponding to a sector of the matrix, and a MOS transistor of the P-channel depletion type with enhanced gate oxide, wherein the MOS transistor is disposed between the output terminal and the pull-down transistor; and a voltage generator incorporating a charge pump; and a switching device including: a main switch connected to a supply voltage reference and the voltage generator, and a set of local switches connected to the main switch, each local switch being associated with a sector of the matrix.

Claim 5

The row decoding circuit of claim 2, wherein the main switch supplies the voltage generator with a regulation voltage and receives a selection voltage value therefrom for the local switches, and wherein the local switches are also input the supply voltage reference.

Claim 6

The row decoding circuit of claim 2, wherein the local switches are actuatable in a mutually exclusive manner.

Claim 7

A row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of a type having a matrix of memory cells laid out as cell rows and columns, the matrix being divided into sectors such that each sector has a corresponding plurality of rows, the row decoding circuit comprising: an input stage that receives input row decode signals and the supply voltages; and an output stage that is driven by the input row decode signals and supply voltages, the output stage having: a complementary pair of high-voltage MOS transistors including a pull-up transistor and a pull-down transistor, wherein the pull-up and pull-down transistors are connected to form an output terminal wherein the output terminal is connected to a plurality of rows corresponding to a sector of the matrix, and a MOS transistor of the P-channel depletion tape with enhanced gate oxide, wherein the MOS transistor is disposed between the output terminal and the pull-down transistor; and a voltage regulator effective to produce a drive voltage for driving a control terminal of the pull-up transistor, the regulator including: a current generator formed of a set of high-voltage P-channel MOS transistors connected to one another to form at least one current mirror, and a series of enable transistors adapted to receive actuation signals on their control terminals.

Claim 8

A row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of a type having a matrix of memory cells laid out as cell rows and columns, the matrix being divided into sectors such that each sector has a corresponding plurality of rows, the row decoding circuit comprising: an input stage that receives input row decode signals and the supply voltages; and an output stage that is driven by the input row decode signals and supply voltages, the output stage having: a complementary pair of high-voltage MOS transistors including a pull-up transistor and a pull-down transistor, wherein the pull-up and pull-down transistors are connected to form an output terminal wherein the output terminal is connected to a plurality of rows corresponding to a sector of the matrix, and a MOS transistor of the P-channel depletion tape with enhanced gate oxide, wherein the MOS transistor is disposed between the output terminal and the pull-down transistor; and a voltage regulator effective to produce a drive voltage for driving a control terminal of the pull-up transistor, the regulator including: a current generator formed of a set of high-voltage P-channel MOS transistors connected to one another to form at least one current mirror, and a series of enable transistors adapted to receive actuation signals on their control terminals.

Claim 9

The row decoding circuit of claim 5, wherein one of the set of high-voltage P-channel MOS transistors is of the depletion type and has a source terminal forced to a voltage value of 0 volts.

Claim 10

The row decoding circuit of claim 5, wherein a drive voltage is picked up by control terminals of the at least one current mirror of the current generator.

Claim 11

A row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of a type having a matrix of memory cells laid out as cell rows and columns, the matrix being divided into sectors such that each sector has a corresponding plurality of rows, the row decoding circuit comprising: an input stage that receives input row decode signals and the supply voltages; and an output stage that is driven by the input row decode signals and supply voltages, the output stage having: a complementary pair of high-voltage MOS transistors including a pull-up transistor and a pull-down transistor, wherein the pull-up and pull-down transistors are connected to form an output terminal, wherein the output terminal is connected to a plurality of rows corresponding to a sector of the matrix, and a MOS transistor of the P-channel depletion type with enhanced gate oxide, wherein the MOS transistor is disposed between the output terminal and the pull-down transistor; and at the end of each row, a row diode having a first end connected to the end of the row, and a second end connected to a node adapted to receive a negative voltage from a negative charge pump.

Claim 12

A row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of a type having a matrix of memory cells laid out as cell rows and columns, the matrix being divided into sectors such that each sector has a corresponding plurality of rows, the row decoding circuit comprising: an input stage that receives input row decode signals and the supply voltages; and an output stage that is driven by the input row decode signals and supply voltages, the output stage having: a complementary pair of high-voltage MOS transistors including a pull-up transistor and a pull-down transistor, wherein the pull-up and pull-down transistors are connected to form an output terminal, wherein the output terminal is connected to a plurality of rows corresponding to a sector of the matrix, and a MOS transistor of the P-channel depletion type with enhanced gate oxide, wherein the MOS transistor is disposed between the output terminal and the pull-down transistor; and at the end of each row, a row diode having a first end connected to the end of the row, and a second end connected to a node adapted to receive a negative voltage from a negative charge pump.

Claim 13

The row decoding circuit of claim 8, wherein the row diode at the end of each row is formed of a high-voltage P-channel MOS transistor of the "nofield" type in a diode configuration.

Claim 14

The row decoding circuit of claim 8, wherein the row diode of each row is located inside a well biased by a signal which is forced to ground when sectors of the matrix are erased.