Non-volatile memory array that enables simultaneous read and write operations

Claim 2

A flash memory device, comprising: an array of flash memory cells; a set of write bit lines; a set of read bit lines; a plurality of switching elements connected to said flash memory cells and said write bit lines or said read bit lines so that each flash memory cell can be selectively coupled to one of said write bit lines or one of said read bit lines; and a plurality of interconnection lines, each interconnection line connected to one of said flash memory cells and two switching elements.

Claim 3

A flash memory device according to claim 1, wherein: said switching elements are transistors.

Claim 4

A flash memory device according to claim 1, wherein: each switching element is connected to only one of either said write bit lines or said read bit lines.

Claim 5

A flash memory device according to claim 1, further comprising: a set of selection lines connected to said switching elements for controlling whether a selected one of said flash memory cells is coupled to one of said write bit lines or one of said read bit lines.

Claim 6

A flash memory device, comprising: an array of flash memory cells; a set of write bit lines; a set of read bit lines; a plurality of switching elements connected to said flash memory cells, at least a first subset of said switching elements are connected to said read bit lines and selectively couple said read bit lines to said flash memory cells, at least a second subset of said switching elements are connected to said write bit lines and selectively couple said write bit lines to said flash memory cells; and a plurality of interconnection lines, each interconnection line connected to one of said flash memory cells, one switching element from said first subset and one switching element from said second subset.

Claim 7

A flash memory device, comprising: an array of flash memory cells; a set of write bit lines; a set of read bit lines; a plurality of switching elements connected to said flash memory cells, at least a first subset of said switching elements are connected to said read bit lines and selectively couple said read bit lines to said flash memory cells, at least a second subset of said switching elements are connected to said write bit lines and selectively couple said write bit lines to said flash memory cells; and a plurality of interconnection lines, each interconnection line connected to one of said flash memory cells, one switching element from said first subset and one switching element from said second subset.

Claim 8

A flash memory device according to claim 5, wherein: said switching elements are transistors.

Claim 9

A flash memory device according to claim 5, wherein: said first subset of switching elements are not connected to said write bit lines; and said second subset of switching elements are not connected to said read bit lines.

Claim 10

A flash memory device according to claim 5, wherein: each flash memory cell is connected to one switching element from said first subset and one switching element from said second subset.

Claim 11

A flash memory device according to claim 5, further comprising: a set of selection lines connected to said switching elements for controlling whether a selected one of said flash memory cells is coupled to one of said write bit lines or one of said read bit lines.

Claim 12

A flash memory device comprising: a set of write bit lines; a set of read bit lines; two or more units, each unit being connected to said set of write bit lines and said set of read bit lines, each unit includes: a plurality of flash memory cells, a plurality of switching elements, each switching element connected to one of said flash memory cells and at least one of said write bit lines or one of said read bit lines so that each flash memory cell of said plurality of flash memory cells can be selectively coupled to one of said write bit lines or one of said read bit lines; and a plurality of interconnection lines, each interconnection line connected to one of said flash memory cells and two switching elements.

Claim 13

A flash memory device comprising: a set of write bit lines; a set of read bit lines; two or more units, each unit being connected to said set of write bit lines and said set of read bit lines, each unit includes: a plurality of flash memory cells, a plurality of switching elements, each switching element connected to one of said flash memory cells and at least one of said write bit lines or one of said read bit lines so that each flash memory cell of said plurality of flash memory cells can be selectively coupled to one of said write bit lines or one of said read bit lines; and a plurality of interconnection lines, each interconnection line connected to one of said flash memory cells and two switching elements.

Claim 14

A flash memory device according to claim 10, wherein: each unit is a sector.

Claim 15

A flash memory device according to claim 10, further comprising: a sense amplifier in communication with said write bit lines and said read bit lines.

Claim 16

A flash memory device according to claim 10, wherein: said switching elements are transistors.

Claim 17

A flash memory device according to claim 10, further comprising: a set of selection lines connected to said switching elements for controlling whether a selected one of said flash memory cells is coupled to one of said write bit lines or one of said read bit lines.

Claim 18

A flash memory device according to claim 10, wherein: each switching element is connected to only one of either said write bit lines or said read bit lines.

Claim 19

A flash memory device, comprising: a first write bit line; a first read bit line; a first selection line; a second selection line; a third selection line; a fourth selection line; a first flash memory cell; a second flash memory cell; a first pass gate connected to said first flash memory cell, said first selection line and said first write bit line so that when said first selection line is activated said first pass gate couples said first flash memory cell to said first write bit line; a second pass gate connected to said second flash memory cell, said second selection line and said first write bit line so that when said second selection line is activated said second pass gate couples said second flash memory cell to said first write bit line; a third pass gate connected to said first flash memory cell, said third selection line and said first read bit line so that when said third selection line is activated said third pass gate couples said first flash memory cell to said first read bit line; a fourth pass gate connected to said second flash memory cell, said fourth selection line and said first read bit line so that when said fourth selection line is activated said fourth pass gate couples said second flash memory cell to said first read bit line; a first interconnection line connected to said first pass gate, said third pass gate and said first memory cell; and a second interconnection line connected to said second pass gate, said fourth pass gate and said second memory cell.

Claim 20

A flash memory device, comprising: a first write bit line; a first read bit line; a first selection line; a second selection line; a third selection line; a fourth selection line; a first flash memory cell; a second flash memory cell; a first pass gate connected to said first flash memory cell, said first selection line and said first write bit line so that when said first selection line is activated said first pass gate couples said first flash memory cell to said first write bit line; a second pass gate connected to said second flash memory cell, said second selection line and said first write bit line so that when said second selection line is activated said second pass gate couples said second flash memory cell to said first write bit line; a third pass gate connected to said first flash memory cell, said third selection line and said first read bit line so that when said third selection line is activated said third pass gate couples said first flash memory cell to said first read bit line; a fourth pass gate connected to said second flash memory cell, said fourth selection line and said first read bit line so that when said fourth selection line is activated said fourth pass gate couples said second flash memory cell to said first read bit line; a first interconnection line connected to said first pass gate, said third pass gate and said first memory cell; and a second interconnection line connected to said second pass gate, said fourth pass gate and said second memory cell.

Claim 21

A flash memory device according to claim 16, wherein: said first pass gate is a first transistor; said second pass gate is a second transistor; said third pass gate is a third transistor; and said fourth pass gate is a fourth transistor.

Claim 22

A flash memory device according to claim 16, further comprising: a second write bit line; a second read bit line; a third flash memory cell; a fourth flash memory cell; a fifth pass gate connected to said third flash memory cell, said first selection line and said second write bit line so that when said first selection line is activated said fifth pass gate couples said third flash memory cell to said second write bit line; a sixth pass gate connected to said fourth flash memory cell, said second selection line and said second write bit line so that when said second selection line is activated said sixth pass gate couples said fourth flash memory cell to said second write bit line; a seventh pass gate connected to said third flash memory cell, said third selection line and said second read bit line so that when said third selection line is activated said seventh pass gate couples said third flash memory cell to said second read bit line; and a eighth pass gate connected to said fourth flash memory cell, said fourth selection line and said second read bit line so that when said fourth selection line is activated said eighth pass gate couples said fourth flash memory cell to said second read bit line.