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US5847424A Expired / Lapsed US ⏱️ 0.0 years remaining

Capacitor of semiconductor memory device and manufacturing method thereof

Assignee: Samsung Electronics Co Ltd
•
Filing: 1996-01-24
•
Granted: 1998-12-08
•
Expires: 2016-01-24
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Abstract

Abstract A capacitor structure of a DRAM device and a method thereof, including a first electrode formed in each unit memory cell to be connected to a source of a transistor, a deteriorating prevention film formed at the lowermost surface of the first electrode, exclusive of a portion where the first electrode is connected to the source of a transistor, an underlayer formed beneath the deterioration prevention film, an undercut formed between the underlayer and deterioration prevention film, a high-dielectric film formed on surfaces of the first electrode, underlayer and deterioration prevention film which is exposed by the undercut, a reaction/diffusion prevention film formed on the high-dielectric film, formed on the first electrode and underlayer, exclusive of an area around the undercut, and a second electrode formed on the entire surface of the high-dielectric film and reaction/diffusion prevention film, thereby preventing increase of leakage current amount caused by the undercut formed during the capacitor manufacturing process.

Inventors

  • 👤 Ho-kyu Kang

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 14:22
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10D; H10D1/00; H10D1/60; H10D1/68

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 177 words
A capacitor for a unit memory cell of a semiconductor memory device, comprising: a substrate having a transistor formed thereon, said transistor including a source/drain; an insulator formed on said substrate and said transistor; a contact hole formed in said insulator to expose the source of said transistor; a first electrode formed on said insulator and connected to the source of said transistor through said contact hole; a deterioration prevention film formed on a lower surface of said first electrode and a top surface of said insulator, wherein said deterioration prevention film has a first lower surface portion contacting said top surface of said insulator and a second lower surface portion spaced apart from said top surface of said insulator by an undercut located below said lower surface of the first electrode; a high permittivity dielectric film formed on surfaces of said first electrode, insulator and deterioration prevention film; a barrier metal film formed on the high permittivity film on said first electrode; and a second electrode formed on the entire surface of the barrier metal film.
Claim 2
Dependent Claim 177 words
A capacitor for a unit memory cell of a semiconductor memory device, comprising: a substrate having a transistor formed thereon, said transistor including a source/drain; an insulator formed on said substrate and said transistor; a contact hole formed in said insulator to expose the source of said transistor; a first electrode formed on said insulator and connected to the source of said transistor through said contact hole; a deterioration prevention film formed on a lower surface of said first electrode and a top surface of said insulator, wherein said deterioration prevention film has a first lower surface portion contacting said top surface of said insulator and a second lower surface portion spaced apart from said top surface of said insulator by an undercut located below said lower surface of the first electrode; a high permittivity dielectric film formed on surfaces of said first electrode, insulator and deterioration prevention film; a barrier metal film formed on the high permittivity film on said first electrode; and a second electrode formed on the entire surface of the barrier metal film.
Claim 3
Dependent Claim 23 words
A capacitor for a semiconductor memory device, according to claim 1, wherein said first and said second electrodes are formed of polycrystalline silicon.
Claim 4
Dependent Claim 23 words
A capacitor for a semiconductor memory device, according to claim 1, wherein said deterioration prevention film is formed of a silicon nitride film.
Claim 5
Dependent Claim 34 words
A capacitor for a semiconductor memory device according to claim 1, wherein said barrier metal film is formed of one material selected from the group consisting of titanium nitride, tungsten nitride, and tungsten silicide.
Claim 6
Dependent Claim 19 words
A capacitor for a semiconductor memory device, according to claim 1, wherein said insulator is formed of silicon dioxide.

References Cited (Backward Citations)

US5459345A Cited
US5567964A Cited
US5497016A Cited
US5559666A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-12-07 2002-06-08 2002-12-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-12-07 2006-06-08 2006-12-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-12-07 2010-06-08 2010-12-08 $7700.00 Window Closed / Lapsed

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