Modular audio data processing architecture

Claim 2

A data processing system operable to process a data stream, comprising an input buffer operable to receive and store the input data stream; from said control processor while said control processor simultaneously processes a second portion of said audio data, said execution controller farther operable to determine a breakpoint between said portion of audio data and a portion of ancillary data and to load an ancillary pointer with a location in the in-put buffer corresponding to the break-point; a multiplier accumulator coupled to said execution controller and operable to perform said processing of the data received from said control processor as directed by said execution controller; and an auxiliary handler coupled to said input buffer and operable to retrieve said ancillary data from said input buffer according to said ancillary pointer and to output said retrieved ancillary data.

Claim 3

The system of claim 1 wherein said processing comprises dequantization, transformation and filtering of the data stream in order to decode said audio data.

Claim 4

The system of claim 1 wherein said processing comprises quantization and transformation of the data stream in order to encode a data stream.

Claim 5

The system of claim 1 and further comprising an output buffer coupled to said control processor and operable to receive and store processed data from said control processor and to output said processed data as an output data stream simultaneously while said input buffer receives and stores said input data stream.

Claim 6

The system of claim 1 and further comprising a first microcode memory coupled to said control processor and operable to store sequences of instructions directing the operation of said control processor.

Claim 7

The system of claim 5 and further comprising a second microcode memory coupled to said execution controller and operable to store sequences of instructions directing the operation of said execution controller.

Claim 8

The system of claim 1 and further comprising a status register coupled to control processor and operable to store and output status information comprising information indicating the synchronization state of the system relative to the data stream, wherein said status register is accessible by an external system which is connected to said data processing system.

Claim 9

The data processing system of claim 1, wherein said ancillary handler is operable to retrieve said ancillary data simultaneously while said control processor processes said first portion of said audio data.

Claim 10

The data processing system of claim 8, wherein said ancillary handler is operable to retrieve said ancillary data in a manner that avoids accessing of said ancillary data by said control processor, whereby said control processor is not burdened with processing said ancillary data.

Claim 11

The data processing system of claim 9, further comprising a flag circuit connected to said ancillary handler and operable to inform said control processor that said ancillary data has been completely retrieved from said input buffer.

Claim 12

A data processing system operable to process a data stream comprising multiplexed audio and auxiliary data, the system comprising: an input buffer operable to receive and store the input data stream; a control processor circuit coupled to the input buffer and operable to retrieve audio data from the input buffer, said control processor further operable to process a first portion of said audio data; an execution controller circuit coupled to said control processor and to direct dequantization, transformation, and filtering of the data received from said control processor while said control processor simultaneously processes a second portion of said audio data; a multiplier accumulator circuit coupled to said execution controller and operable to perform said dequantization, transformation, and filtering of the data received from said control processor as directed by said execution controller; an ancillary handler circuit coupled to said input buffer and operable to retrieve ancillary data from said input buffer and to output said retrieved ancillary data; an output buffer coupled to said control processor and operable to receive and store processed data from said control processor; first microcode memory coupled to said control processor and operable to store sequences of instructions directing the operation of said control processor; second microcode memory coupled to said execution controller and operable to store sequences of instructions directing the operation of said execution controller; and a status register coupled to control processor and operable to store and output status information comprising information indicating the synchronization state of the system relative to the data stream.

Claim 13

A data processing system operable to process a data stream comprising multiplexed audio and auxiliary data, the system comprising: an input buffer operable to receive and store the input data stream; a control processor circuit coupled to the input buffer and operable to retrieve audio data from the input buffer, said control processor further operable to process a first portion of said audio data; an execution controller circuit coupled to said control processor and to direct dequantization, transformation, and filtering of the data received from said control processor while said control processor simultaneously processes a second portion of said audio data; a multiplier accumulator circuit coupled to said execution controller and operable to perform said dequantization, transformation, and filtering of the data received from said control processor as directed by said execution controller; an ancillary handler circuit coupled to said input buffer and operable to retrieve ancillary data from said input buffer and to output said retrieved ancillary data; an output buffer coupled to said control processor and operable to receive and store processed data from said control processor; first microcode memory coupled to said control processor and operable to store sequences of instructions directing the operation of said control processor; second microcode memory coupled to said execution controller and operable to store sequences of instructions directing the operation of said execution controller; and a status register coupled to control processor and operable to store and output status information comprising information indicating the synchronization state of the system relative to the data stream.