Synthetic aperture radar digital signal processor

Claim 2

A digital signal processor to be used in conjunction with an addressable memory device, the processor comprising: an arithmetic unit having first and second data inputs and first and second reference inputs, the arithmetic unit including: an I-channel datapath and a Q-channel datapath, each datapath including a multiplier/accumulator, a multiplier and an adder, the inputs to each multiplier/accumulator being derived from said data inputs and said first reference input, the inputs to each multiplier being derived from the output of the multiplier/accumulator for that channel and said second reference input, the inputs to each adder being derived from the output of the multiplier for that channel and said data inputs, the outputs of said adders being combined to form a result; a control unit including at least one address generator operative to generate an address to said memory device, enabling said memory to provide a reference or a data input to said arithmetic unit; and a user-programmable control sequencer connected to the address generator, the arithmetic unit and the memory, the sequencer being operative to coordinate and control the functioning of the arithmetic unit and cause the address generator to generate an address for said memory.

Claim 3

The digital signal processor of claim 1 wherein said control unit includes a plurality of address generators, at least one being associated with providing a data input to the arithmetic unit, and with at least one being associated with providing a reference input to the arithmetic unit.

Claim 4

The digital signal processor of claim 2 wherein each address generator is implemented with a digital differential analyzer.

Claim 5

The digital signal processor of claim 1 wherein said control section further includes an I/O controller connected to the control sequencer and the address generator, the I/O controller being operative to manage data, address and control signals required by, and generated by, said processor in conjunction with external devices in a system-level implementation.

Claim 6

In a digital signal processor of the type having two channels, each with a multiplier/accumulator fed by first and second data inputs and a first reference input, the improvement comprising: a second reference input; a pair of multipliers following the multiplier/accumulators, each multiplier being associated with a channel, one input to the multiplier associated with the first channel being the output of the first-channel multiplier/accumulator, one input to the multiplier associated with the second channel being the output of the second-channel multiplier/accumulator, and the other input to each multiplier being the second reference input; and a pair of adders following the second multipliers, each adder being associated with a channel, one input to the adder associated with the first channel being the output of the first-channel multiplier, one input to the adder associated with the second channel being the output of the second-channel multiplier, the other adder inputs being said data inputs.

Claim 7

In a digital signal processor of the type having two channels, each with a multiplier/accumulator fed by first and second data inputs and a first reference input, the improvement comprising: a second reference input; a pair of multipliers following the multiplier/accumulators, each multiplier being associated with a channel, one input to the multiplier associated with the first channel being the output of the first-channel multiplier/accumulator, one input to the multiplier associated with the second channel being the output of the second-channel multiplier/accumulator, and the other input to each multiplier being the second reference input; and a pair of adders following the second multipliers, each adder being associated with a channel, one input to the adder associated with the first channel being the output of the first-channel multiplier, one input to the adder associated with the second channel being the output of the second-channel multiplier, the other adder inputs being said data inputs.

Claim 8

The digital signal processor of claim 5, the improvement further comprising: a holding register connected between the data inputs and the multiplier/accumulators, the holding register enabling the processor to perform a complex-by-complex multiplication upon said data.

Claim 9

The digital signal processor of claim 5, the improvement further comprising: four holding registers, one associated with each input to each adder, the holding registers enabling the processor to perform a complex multiplication during the zero-th stage of a fast Fourier transformation.

Claim 10

The digital signal processor of claim 5, the improvement further comprising: at least one address generator to be used in conjunction with a memory unit; and a user-programmed control unit connected to said arithmetic unit and the address generator, the control unit being operative to cause said generator to derive an address for said memory unit, the data stored at that address being used as an input to the arithmetic unit.

Claim 11

A digital signal processor optimized for synthetic aperture radar image formation adapted for use in conjunction with a memory device, the processor comprising: a first data-input port; a second data-input port; data-select logic connected to said first and said second data input ports, said logic being operative to output the data from either port to any of a first-stage I channel, a first-stage Q channel, a second-stage I channel or a second-stage Q channel; a first-stage reference input port; reference-path logic having a first input to receive data from said first-stage reference input port, a second input to receive data from said first-stage I channel, and a third input adapted to receive data from said first-stage Q channel, said reference-path logic being operative to route any one of said inputs to either a first output or a second output; swapping logic having a first input to receive data from said first-stage I channel and a second input to receive data from said first-stage Q channel, said swapping logic being operative to output either of said inputs to either a first output or a second output; a first multiplier stage having a first multiplier/accumulator and a second multiplier/accumulator, each with two inputs, the inputs to the first multiplier/accumulator being the first output of said swapping logic and the first output of said reference-path logic, the inputs to the second multiplier/accumulator being the second output of said swapping logic and the second output of said reference-path logic; a second-stage reference input port; a second multiplier stage having a first multiplier and a second multiplier, each with two inputs, one input to the first multiplier being the output of the first multiplier/accumulator, one input to the second multiplier being the output of the second multiplier/accumulator, and the other input to each multiplier being connected to said second-stage reference input port; and a first negate/pass circuit connected to the output of the first multiplier, and a second negate/pass circuit connected to the output of the second multiplier, each negate/pass circuit being operative to produce an output by either negating its input or by passing its input through unchanged; a first adder and a second adder, each with two inputs, one input to the first adder being the output of the first negate/pass circuit, the other input to the first adder being the second-stage I-channel, one input to the second adder being the output of the second negate/pass circuit, the other input to the second adder being the second-stage Q-channel; an output scaler connected to the outputs of the adders, the output scaler being operative to numerically scale its inputs and provide an output to an output data port; a plurality of digital differential analyzers configured as data and reference address generators, the generators being operative to provide addresses to said memory device, the contents of the memory thus retrieved being used as said data and reference inputs; an I/O controller operative to manage data, address and control signals required by, and generated by, said processor in conjunction with external devices; and a user-programmable control sequencer connected to the data-select logic, reference path logic, swapping logic, multiplier/accumulators, multipliers, negate/pass circuits, adders, output scaler, digital differential analyzers, I/O controller and memory device , the sequencer being operative to coordinate and control the overall functioning of said processor and cause said address generators to generate data and reference addresses.

Claim 12

A digital signal processor optimized for synthetic aperture radar image formation adapted for use in conjunction with a memory device, the processor comprising: a first data-input port; a second data-input port; data-select logic connected to said first and said second data input ports, said logic being operative to output the data from either port to any of a first-stage I channel, a first-stage Q channel, a second-stage I channel or a second-stage Q channel; a first-stage reference input port; reference-path logic having a first input to receive data from said first-stage reference input port, a second input to receive data from said first-stage I channel, and a third input adapted to receive data from said first-stage Q channel, said reference-path logic being operative to route any one of said inputs to either a first output or a second output; swapping logic having a first input to receive data from said first-stage I channel and a second input to receive data from said first-stage Q channel, said swapping logic being operative to output either of said inputs to either a first output or a second output; a first multiplier stage having a first multiplier/accumulator and a second multiplier/accumulator, each with two inputs, the inputs to the first multiplier/accumulator being the first output of said swapping logic and the first output of said reference-path logic, the inputs to the second multiplier/accumulator being the second output of said swapping logic and the second output of said reference-path logic; a second-stage reference input port; a second multiplier stage having a first multiplier and a second multiplier, each with two inputs, one input to the first multiplier being the output of the first multiplier/accumulator, one input to the second multiplier being the output of the second multiplier/accumulator, and the other input to each multiplier being connected to said second-stage reference input port; and a first negate/pass circuit connected to the output of the first multiplier, and a second negate/pass circuit connected to the output of the second multiplier, each negate/pass circuit being operative to produce an output by either negating its input or by passing its input through unchanged; a first adder and a second adder, each with two inputs, one input to the first adder being the output of the first negate/pass circuit, the other input to the first adder being the second-stage I-channel, one input to the second adder being the output of the second negate/pass circuit, the other input to the second adder being the second-stage Q-channel; an output scaler connected to the outputs of the adders, the output scaler being operative to numerically scale its inputs and provide an output to an output data port; a plurality of digital differential analyzers configured as data and reference address generators, the generators being operative to provide addresses to said memory device, the contents of the memory thus retrieved being used as said data and reference inputs; an I/O controller operative to manage data, address and control signals required by, and generated by, said processor in conjunction with external devices; and a user-programmable control sequencer connected to the data-select logic, reference path logic, swapping logic, multiplier/accumulators, multipliers, negate/pass circuits, adders, output scaler, digital differential analyzers, I/O controller and memory device , the sequencer being operative to coordinate and control the overall functioning of said processor and cause said address generators to generate data and reference addresses.

Claim 13

The digital signal processor of claim 9 further including: a holding register in said first-stage I channel and said first-stage Q channel, said register being operative to enable said processor to perform a complex-by-complex multiplication upon said input data in accordance with a control signal from said control sequencer; and a holding register in said second-stage I-channel and said second-stage Q channel and a holding register connected between the second-stage multipliers and the negate/pass circuits, the holding registers being operative to enable said processor to perform a complex multiplication during the zero-th stage of a fast Fourier transformation in accordance with a control signal from said control sequencer.

Claim 14

The digital signal processor of claim 10 wherein said processor is implemented as a single-chip integrated circuit.

Claim 15

The digital signal processor of claim 11 wherein said integrated circuit is fabricated using a C-MOS process.