Synchronization circuit for ATM cells

Claim 2

A synchronization circuit comprised of: a shift register unit (21) which receives and holds in a bit serial manner input bit trains (Bin) constituting ATM cells used for data transmission; a continuous CRC arithmetic unit (22) which continuously performs a CRC operation in a bit serial manner in accordance with a simplified CRC operation process comprised of a usual CRC operation process modified in advance to reduce the amount of operations; and a synchronization control unit (23) which receives as input the CRC arithmetic operation result (e out ) from the said continuous CRC arithmetic unit (22), transmits, at the ATM cell transmission side, the CRC arithmetic operation result (C out ) as the synchronization establishment signal (S e ) in the said ATM cells and outputs, at the ATM reception side, the operation result as a synchronization detection signal (S d ) when the CRC arithmetic operation result (C out ) transmitted from the transmission side and the CRC arithmetic operation result (C out ) obtained by the operation at the continuous CRC arithmetic unit (22) match.

Claim 3

A synchronization circuit as set forth in claim 1, wherein said shift register unit (21) is comprised of a shift register of m (m being an integer of 2 or more and the number of bits covered by the said CRC operation) bit length; said continuous CRC arithmetic unit (22) is comprised of a first CRC arithmetic unit (31) which deems the overflow bits forced out from said shift register as the term of the m-th order, divides the term of the m-th order by a generator polynomial used for the CRC operation, and outputs the remainder which is obtained as a first CRC arithmetic operation result, a second CRC arithmetic unit (32) which receives as input an input bit train divided at the input stages of the shift register, deems the bit appearing at the divided input bit train side as the term of the 0-th order, and outputs as the second CRC arithmetic operation result the term of the 0-th order plus the remainder obtained by dividing the CRC arithmetic operation result obtained just before by the said generator polynomial, and a subtraction unit (33) which obtains the difference between said first CRC arithmetic operation result and said second CRC arithmetic operation result and obtains the said CRC arithmetic operation result in a time series manner from said subtraction unit (33) and outputs it to the said synchronization control unit (23).

Claim 4

A synchronization circuit as set forth in claim 2, wherein said first CRC arithmetic unit (31) and said second CRC arithmetic unit (32) are comprised by a single CRC arithmetic unit (35); said subtraction unit (33) is comprised of a CRC memory unit (36); and said CRC arithmetic unit (35) receives as input the output of said shift register, the output appearing at the said divided input bit train side, and the CRC arithmetic operation result of just before held in said CRC memory unit, performs the CRC operation, holds the CRC arithmetic operation result in the said CRC memory unit, and outputs the held CRC arithmetic operation result to the said CRC arithmetic unit (35) and the said synchronization control unit (23).

Claim 5

A synchronization circuit as set forth in claim 3, wherein said CRC arithmetic unit (35) is comprised of a read only memory (ROM), receives as address input the output of said shift register, the output appearing at the said divided input bit train side, and the CRC arithmetic operation result of just before held in said CRC memory unit, and reads out the CRC arithmetic operation result corresponding to the address.

Claim 6

A synchronization circuit as set forth in claim 2, wherein said first CRC arithmetic unit (31) is comprised of an arithmetic unit which outputs the CRC arithmetic operation result; said second CRC arithmetic unit (32) is comprised of a CRC operator; said CRC operator is comprised of a plurality of shift registers (12) connected in series, a plurality of EX-OR gates (13) inserted between the shift registers and receiving at the first stage said divided input bit train, and a connector (14) connected to said EX-OR gates and connecting or not connecting the output from the final stage shift register in accordance with coefficients of orders of a generator polynomial, said arithmetic unit receiving as input the output from said shift register unit (21) and the output from the shift registers in said CRC operator; the first stage EX-OR gate in said CRC operator receiving said divided input bit train; and said arithmetic unit operating so as to obtain the EX-OR of the remainder R[ χ m /G] (where G is the generator polynomial and x "' is the term of the m-th order; R[ χ m /G]= χ m mod(G)) and the output of said shift registers when the output of the shift register unit is "1", operates to output the remainder as is when it is "0", and operates to load the output operation result in the shift registers once again.

Claim 7

A synchronization circuit as set forth in claim 2, wherein said first CRC arithmetic unit (31) is comprised of a CRC operator which outputs a CRC arithmetic operation result, said second CRC arithmetic unit (32) is comprised of an output unit which outputs a remainder R-[ x m /G] (where G is a generator polynomial and x`" is a term of an m-th order; R[ χ m /G]= χ m mod(G)); said output unit receives as input the output from the said shift register unit and outputs a remainder R; and said CRC operator is comprised of a plurality of shift registers (12) connected in series, a plurality of EX-OR gates (13) inserted between the shift registers and receiving at the first stage said divided input bit train, and a connector (14) connected to said EX-OR gates and connecting or not connecting the output from the final stage shift register in accordance with coefficients of orders of a generator polynomial.

Claim 8

A synchronization circuit as set forth in claim 1, wherein said shift register unit (21) is comprised of a shift register of m (m being an integer of 2 or more and the number of bits covered by the CRC operation) bit length and said continuous CRC arithmetic unit (22) is comprised of a third CRC arithmetic unit (41) which divides the first bit train, delayed by m bits by the said shift register and deemed a term of an m-th order, by the generator polynomial used for the said CRC operation and outputs the remainder obtained as the third CRC arithmetic operation result, a fourth CRC arithmetic unit (42) which divides a second bit train, deemed to be the same bit train as said first bit train with the same bit train as the bit train stored in the said shift register attached to the bottom portion, by said generator polynomial and outputs the remainder obtained as the fourth CRC arithmetic operation result, and a subtraction unit (43) which obtains a difference between said third CRC arithmetic operation result and said fourth CRC arithmetic operation result and obtains the said CRC arithmetic operation results in a time series manner from said subtraction unit (43) and outputs the same to said synchronization control unit (23).

Claim 9

A synchronization circuit as set forth in claim 7, wherein said subtraction unit (43) is comprised of an EX-OR processing unit (44) which obtains the EX-OR of the outputs from the said third and fourth CRC arithmetic units (41, 42).

Claim 10

A synchronization circuit as set forth in claim 7, wherein said third CRC arithmetic unit (41) is comprised of a first read only memory (ROM) and a CRC memory unit which holds the output of the first ROM, said first ROM receiving the output of the said CRC memory unit and the output of the shift register unit as address input and outputting the CRC arithmetic operation result corresponding to the address and said fourth CRC arithmetic unit (42) is comprised of a second read only memory (ROM) and a CRC memory unit which holds the output of the second ROM, said second ROM receiving the output of the said CRC memory unit and said input bit train as address input and outputting the CRC arithmetic operation result corresponding to the address.

Claim 11

A synchronization circuit as set forth in claim 9, wherein said first read only memory and said second read only memory are comprised of a single read only memory which sums up the same in one.

Claim 12

A synchronization circuit as set forth in claim 8, wherein said third CRC arithmetic unit (41) is comprised of an output unit which receives as input the output from said shift register unit (21) and outputs a remainder R[ χ m /G] (where G is a generator polynomial and x is a term of the m-th order); R[ χ m /G]= χ m mod(G)) and a first CRC operator; said fourth CRC arithmetic unit (42) is comprised of a second CRC operator which receives said input bit train; said EX-OR processing unit (44) is realized by an output unit (46) which outputs a remainder R-[ χ m /G]; and said first and second CRC operators are respectively comprised of a plurality of serially connected shift registers (12); EX-OR gates (13) inserted between the shift registers; and a connector which is connected to the EX-OR gates and connects or does not connect the output from the final stage shift register in accordance with coefficients of orders of the gene rator polynomial.

Claim 13

A synchronization circuit as set forth in claim 1, wherein said shift register unit (21) is comprised of a shift register of m (m being an integer of 2 or more and the number of bits covered by the said CRC operation) bit length and said continuous CRC arithmetic unit (22) is comprised of a wired logic unit (51) which receives as input m number of bit outputs (b) from the shift register and distributes the bit outputs (b) to predetermined bit positions set in advance for the bit outputs (b) among a plurality of bit positions and a remainder arithmetic unit (52) which executes the addition of the bit outputs (b) distributed to each of the plurality of input gates (53) corresponding to the plurality of bit positions and input to each of the input gates (53), performs an equivalent operation as the said CRC operation on the said input bit train (B;"), and outputs said CRC arithmetic operation result (Cout) and outputs the said CRC arithmetic operation result (Cout) to the said synchronization control unit (23).

Claim 14

A synchronization circuit as set forth in claim 12, wherein said remainder arithmetic unit (52) is comprised of a parity check circuit (PC).

Claim 15

A synchronization circuit as set forth in claim 1, wherein said shift register unit (21) is comprised of a k-stage shift register (where k is a specific natural number of 1 or more which is less than the number of bits of the octets constituting the headers of the ATM cells) and said continuous CRC arithmetic unit (22) is comprised of a remainder arithmetic unit (61) which receives as input the first stage bit output (Do) and the k-th stage bit output (Ds) of the k-stage shift register and the CRC arithmetic operation result (C n-1 ) obtained by the CRC operation just before and calculates the CRC arithmetic operation result (C n ) and a delay unit (62) which gives a delay to the said CRC arithmetic operation result (C n ) output from the remainder arithmetic unit (61) and returns it as the CRC arithmetic operation result (C n-1 ) of the time when obtaining the CRC arithmetic operation result to the remainder arithmetic unit (62) and divides the said CRC arithmetic operation result (C n ) output from the remainder arithmetic unit (61) and supplies it to the said synchronization control unit (23).

Claim 16

A synchronization circuit as set forth in claim 14, wherein said delay unit (62) is comprised of a D-flipflop and applies a timing clock the same as the timing clock applied to the said k-stage shift register to the said D-flipflop.

Claim 17

A synchronization circuit as set forth in claim 14, wherein said remainder arithmetic unit (61) is comprised of a wired logic unit (63), a plurality of EX-OR gates (64), and leading wires (65) which send out the said CRC arithmetic operation result; said wired logic unit is comprised of a first wire group which receives the first-stage output and k-th stage output of the k-stage shift register and the output of the said delay unit (62) and a second wire group which is connected by a predetermined bit pattern to the first wire group and reaches to the input of the said EX-OR gates; and said leading wires are connected to the output of the EX-OR gates.

Claim 18

A synchronization circuit as set forth in claim 1, wherein said synchronization control unit (23) is provided with a reset means (70), the internal states of the shift register unit (21) and continuous CRC arithmetic unit (22) are reset by the reset signal (R/S) output from said reset means (70), and said reset means (70) outputs said reset signal (R/s) cyclically in synchronization with the header of said ATM cells.

Claim 19

A synchronization circuit as set forth in claim 17, wherein said reset means (70) in said synchronization control unit (23) is comprised of a hunt processing unit (72), a rear protection unit (73), and a front protection unit (74); said synchronization control unit (23) judges if the CRC arithmetic operation result of the input bit train coincides with the desired value; if coinciding, a coincidence signal is given to the said hunt processing unit and a signal indicating the start of pseudo synchronization is issued; said rear protection unit starts operation after receiving the signal; a synchronization start signal is applied to the said front protection unit if rear protection is confirmed, and said front protection unit issues said synchronization detection signal (S d ) and issues said reset signal.

Claim 20

A synchronization circuit as set forth in claim 17, wherein said shift register unit (21) is comprised of a k-stage shift register (where k is a specific natural number of 1 or more which is less than the number of bits of the octets constituting the headers of the ATM cells) and said continuous CRC arithmetic unit (22) is comprised of a remainder arithmetic unit (61) which receives as input the first-stage bit output (Do) and the k-th stage bit output (0 5 ) of the k-stage shift register and the CRC arithmetic operation result (C n . t ) obtained by the CRC operation just before and calculates the CRC arithmetic operation result (C n ) and a delay unit (62) which gives a delay to the said CRC arithmetic operation result (C n ) output from the remainder arithmetic unit (61) and returns it as the CRC arithmetic operation result (C n-1 ) of the time when obtaining the CRC arithmetic operation result to the remainder arithmetic unit (62) and divides the said CRC arithmetic operation result (C n ) output from the remainder arithmetic unit (61) and supplies it to the said synchronization control unit (23), said synchronization circuit characterized in that said reset means (80) is comprised of an AND gate (75), which AND gate receives at one input a separate reset signal than said reset signal and receives at the other input the output of a header counter which counts the number of arrivals of headers of ATM cells, the output of the AND gate being supplied to the final shift register stage of the k-stage shift register and the delay unit (62) comprised of a D-flipflop as a clock input and said separate reset signal is a signal which rises along with the reception of the said input bit train and falls with the end of the reception.

Claim 21

A synchronization circuit as set forth in claim 1, wherein said synchronization control unit (23) is provided with a header error correction means (80) for correcting the bit error of a header in an ATM cell, said header error correction means (80) being comprised of a portion for cyclically replacing predetermined amounts of bits in the bit train corresponding to the said header to a higher order, a portion for performing a predetermined logical operation while shifting bits successively so as to produce error correction information, and a bit correction portion for correcting one-bit errors in accordance with said error correction information.

Claim 22

A synchronization circuit as set forth in claim 1, wherein said continuous CRC arithmetic unit (22) is provided with a logic inversion means (100) which inverts the logic of a predetermined plurality of bits in a bit train of said CRC arithmetic operation results (C out ), and said predetermined plurality of bits are the number of bits corresponding to the "1" " bits in an offset bit train mapped in an HEC region in the header in the ATM cells in advance at the transmission side.