Data output buffer for memory device

Claim 2

A data output buffer for a memory device having a memory chip, comprising: a detection unit for detecting an external output data and outputting a detection data; a clock signal adjusting unit coupled to the detection unit for comparing the detection data from the detection unit and a data outputted from the memory chip in accordance with an externally applied clock signal and outputting a first signal and a second signal; and an output buffer unit coupled to the clock signal adjusting unit and outputting a data in accordance with the first signal and the second signal.

Claim 3

The data output buffer according to claim 1, wherein the detection unit includes a differential amplifier for receiving a reference voltage and the external output data and performing an amplification operation in accordance with a chip enable signal, thereby outputting the detection data.

Claim 4

The data output buffer according to claim 1, wherein the clock signal adjusting unit includes: a first signal generator outputting the first signal for determining a time to output the first signal in accordance with an externally applied clock signal; an output enable signal generator outputting an output enable signal in accordance with the externally applied clock signal; a data compare unit coupled to the output enable signal generator for comparing the detection data outputted from the detection unit and the data outputted from the memory chip; and a second signal generator coupled to the data compare unit for outputting the second signal enabling the output buffer unit in accordance with outputs from the data compare unit and the output enable signal generator.

Claim 5

The data output buffer according to claim 3, wherein the data compare unit includes: a NAND gate and a first NOR gate performing an inversion OR operation and an inversion AND operation for the detection data outputted from the detection unit and the data outputted from the memory chip; an inverter inverting an output from the NAND gate; and a second NOR gate performing an inversion OR operation for outputs from the inverter and the first NOR gate.

Claim 6

The data output buffer according to claim 3, wherein the second signal generator includes: a first inverter inverting an output from the data compare unit; a first NAND gate performing an inversion AND operation for outputs from the first inverter and the output enable signal generator; a second NAND gate for performing an inversion AND operation for outputs from the data compare unit and the output enable signal generator; a delay unit delaying an output from the second NAND gate; a third NAND gate performing an inversion AND operation for outputs from the delay unit and the first NAND gate; and a second inverter inverting an output from the third NAND gate and outputting an inverted signal to the data output buffer unit.

Claim 7

The data output buffer according to claim 1, wherein the clock signal adjusting unit compares the detection data from the detection unit with the data from the memory chip to determine when to output the second signal enabling the output buffer unit.

Claim 8

The data output buffer according to claim 6, wherein the clock signal adjusting unit determines a time to generate the second signal when the detection data and the data outputted from the memory chip are not identical, by decreasing an operating speed of the output buffer unit, so that the output buffer unit starts operating after an output buffer of another memory chip has been off.

Claim 9

The data output buffer according to claim 6, wherein the clock signal adjusting unit determines a time to generate the second signal when the detection data and the data outputted from the memory chip are identical, by increasing an operating speed of the output buffer unit, so that an output from another memory chip is maintained and a level of the output data does not fall into a termination voltage.