Semiconductor device having a fuse and an improved moisture resistance

Claim 2

A semiconductor device, comprising: a fuse layer; an interlayer insulating layer formed to cover said fuse layer, provided with a concave portion formed on its surface located directly above said fuse layer which concave portion reduces the thickness of the interlayer insulating layer directly above said fuse layer, and having a first opening width (W1) larger than two-dimensional width of said fuse layer; and a passivation layer formed to cover said interlayer insulating layer, provided with a first opening exposing a bottom surface of said concave portion located directly above said fuse layer and having a second opening width (W2) smaller than said first opening width (W1).

Claim 3

The semiconductor device according to claim 1, wherein a metal interconnection layer is formed on a surface of said interlayer insulating layer located around said concave portion, and said passivation layer covers said metal interconnection layer and extends on sidewalls of said concave portion.

Claim 4

The semiconductor device according to claim 1, wherein said passivation layer includes a first insulating layer having a first relative dielectric constant formed to cover said interlayer insulating layer, and a second insulating layer having a second relative dielectric constant higher than said first relative dielectric constant formed to cover said first insulating layer, said first insulating layer is provided with a second opening having sidewalls connected to the sidewalls of said concave portion and penetrating through said first insulating layer, and said second insulating layer extends on the sidewalls of said second opening and the sidewalls of said concave portion to cover an interface between said first insulating layer and said interlayer insulating layer.

Claim 5

The semiconductor device according to claim 3, wherein a bonding pad layer is formed on the surface of said interlayer insulating layer spaced from said concave portion, a third opening having a third opening width (W3) and exposing a surface of said bonding pad layer is formed in said first insulating layer, said second insulating layer extends on the sidewalls of said third opening, and a fourth opening having a fourth opening width (W4) smaller than said third opening width (W3) and exposing a portion of the surface of said bonding pad layer is formed in said second insulating layer located within said third opening.

Claim 6

A semiconductor device, comprising: a fuse layer; an interlayer insulating layer formed to cover said fuse layer, provided with a concave portion formed directly above said fuse layer and having an opening width (W1) larger than the two-dimensional width of said fuse layer which concave portion reduces the thickness of the interlayer insulating layer directly above said fuse layer; and a passivation layer covering said interlayer insulating layer, extending on sidewalls of said concave portion to reach an edge portion of a bottom surface of said concave portion, and exposing the bottom surface of said concave portion located directly above said fuse layer.

Claim 7

A semiconductor device, comprising: a fuse layer; an interlayer insulating layer formed to cover said fuse layer, provided with a concave portion formed directly above said fuse layer and having an opening width (W1) larger than the two-dimensional width of said fuse layer which concave portion reduces the thickness of the interlayer insulating layer directly above said fuse layer; and a passivation layer covering said interlayer insulating layer, extending on sidewalls of said concave portion to reach an edge portion of a bottom surface of said concave portion, and exposing the bottom surface of said concave portion located directly above said fuse layer.

Claim 8

A semiconductor device, comprising: a fuse layer; an interlayer insulating layer formed on a substrate and covering the fuse layer; a bonding pad layer formed on a surface of said interlayer insulating layer; a first insulating layer covering said interlayer insulating layer, having a first opening which exposes a surface of said bonding pad layer, and having a first relative dielectric constant; and a second insulating layer covering said first insulating layer and sidewalls of said first opening, having a second opening which exposes a portion of the surface of said bonding pad layer, and having a second relative dielectric constant higher than said first relative dielectric constant, wherein the openings in the first and second insulating layers expose the interlayer insulating layer located directly above the fuse layer, said interlayer insulating layer having a concave portion directly above said fuse layer which concave portion reduces the thickness of the interlayer insulating layer directly above said fuse layer, and a passivation layer is formed of said first and said second insulating layers.

Claim 9

A semiconductor device, comprising: a fuse layer; an interlayer insulating layer formed on a substrate and covering the fuse layer; a bonding pad layer formed on a surface of said interlayer insulating layer; a first insulating layer covering said interlayer insulating layer, having a first opening which exposes a surface of said bonding pad layer, and having a first relative dielectric constant; and a second insulating layer covering said first insulating layer and sidewalls of said first opening, having a second opening which exposes a portion of the surface of said bonding pad layer, and having a second relative dielectric constant higher than said first relative dielectric constant, wherein the openings in the first and second insulating layers expose the interlayer insulating layer located directly above the fuse layer, said interlayer insulating layer having a concave portion directly above said fuse layer which concave portion reduces the thickness of the interlayer insulating layer directly above said fuse layer, and a passivation layer is formed of said first and said second insulating layers.